公开(公告)号：US06198153B1

公开(公告)日：2001-03-06

申请号：US08840948

申请日：1997-04-21

申请人： Edward W. Liu ,  See-Hoi Caesar Wong

发明人： Edward W. Liu ,  See-Hoi Caesar Wong

IPC分类号： H01L27108

CPC分类号： H01L28/40 ,  H01L27/0629 ,  H01L27/0805

摘要： The present invention provides for a shielded capacitor in a digital CMOS fabrication process. The shield capacitor comprises a first surface (also known as a top plate) and a second surface (the bottom plate). The bottom plate has two portions which are connected, and the two portions of the bottom plate are positioned to sandwich the top plate in between the portions. A polysilicon layer is fabricated between the plates and the substrate of the semiconductor to isolate the plates from the substrate. To build the shielded capacitor, the polysilicon layer is fabricated first, then the plates are built on top of the polysilicon layer. The polysilicon layer is silicized and is often connected to the ground.

摘要翻译： 本发明提供了数字CMOS制造工艺中的屏蔽电容器。 屏蔽电容器包括第一表面（也称为顶板）和第二表面（底板）。 底板具有连接的两个部分，并且底板的两个部分被定位成将顶板夹在两部分之间。 在板和半导体的衬底之间制造多晶硅层以将板与衬底隔离。 为了构建屏蔽电容器，首先制造多晶硅层，然后在多晶硅层的顶部上建立板。 多晶硅层被硅化并且经常连接到地面。

公开(公告)号：US5982229A

公开(公告)日：1999-11-09

申请号：US971428

申请日：1997-11-17

申请人： See-Hoi Caesar Wong ,  Edward Liu

发明人： See-Hoi Caesar Wong ,  Edward Liu

IPC分类号： H03H19/00 ,  H03K5/00

CPC分类号： H03H19/004

摘要： A novel signal processing scheme comprises a digital to analog converter which is clocked at a first frequency, and a switched capacitor filter which receives input from the digital to analog converter and is clocked at a second frequency which is a multiple N times the first frequency. A preferred version of the present invention further comprises an analog signal sychronization circuit which allows the switched capacitor filter to oversample output from the digital to analog converter. The analog signal sychronization circuit comprises a sample and hold circuit, which receives input from the digital to analog converter and holds the input so that the switched capacitor filter can sample the same input N times, and a digital clock generator, which clocks the sample and hold circuit such that the sample and hold circuit only samples settled and valid output data from the digital to analog converter. An RC active filter receives input from the switched capacitor filter and rejects signal images at the first and higher frequencies.

摘要翻译： 一种新颖的信号处理方案包括以第一频率计时的数模转换器和开关电容滤波器，其接收来自数模转换器的输入，并以第一频率倍数N的第二频率进行计时。 本发明的优选方案还包括模拟信号同步电路，其允许开关电容滤波器对来自数模转换器的输出进行过采样。 模拟信号同步电路包括采样和保持电路，其从数模转换器接收输入并保持输入，使得开关电容滤波器可以对相同的输入进行N次采样;以及数字时钟发生器，其对时钟进行采样和 保持电路使得采样和保持电路只从数模转换器采样稳定和有效的输出数据。 RC有源滤波器从开关电容滤波器接收输入，并在第一和更高频率处拒绝信号图像。

公开(公告)号：US06339391B1

公开(公告)日：2002-01-15

申请号：US09459507

申请日：1999-12-13

申请人： Tae-Song Chung ,  See-Hoi Caesar Wong

发明人： Tae-Song Chung ,  See-Hoi Caesar Wong

IPC分类号： H03M182

CPC分类号： H03K17/04106 ,  H03M1/742

摘要： A method and apparatus for optimizing crossover voltage for differential pair switches in a current-steering digital-to-analog converter or the like are disclosed. An array of at least one or more MOSFET switches may be utilized to control the crossover voltage of a differential pair of transistors such that the off time overlap of the differential pair transistors is optimized. In one embodiment, the pull-up and pull-down times of the input for the differential pair transistors are optimized such that the differential pair transistors are not turned off simultaneously. The array of switches may be n-channel MOSFETs when the differential pair are p-channel MOSFETs. Likewise, the array of switches may be p-channel MOSFETs when the differential pair are n-channel MOSFETs. The output of the diflerential pair is free of crossover glitches and is capable of being utilized in a data converter such as a current-steering digital-to-analog converter (DAC).

摘要翻译： 公开了一种用于优化电流转向数模转换器等中的差分对开关的交叉电压的方法和装置。 可以使用至少一个或多个MOSFET开关的阵列来控制差分对晶体管的交叉电压，使得差分对晶体管的关断时间重叠被优化。 在一个实施例中，差分对晶体管的输入的上拉和下拉时间被优化，使得差分对晶体管不同时截止。 当差分对是p沟道MOSFET时，开关阵列可以是n沟道MOSFET。 同样，当差分对是n沟道MOSFET时，开关阵列可以是p沟道MOSFET。 差分对的输出没有交叉故障，并且能够被用在诸如电流转向数模转换器（DAC）的数据转换器中。