公开(公告)号：US08487683B1

公开(公告)日：2013-07-16

申请号：US13356610

申请日：2012-01-23

Applicant: Siddhartha Gopal Krishna ,  Senthil Velan K

Inventor： Siddhartha Gopal Krishna ,  Senthil Velan K

IPC: H03K5/13

CPC classification number: H03K5/13

Abstract: A circuit for generating multi-phase, non-overlapping clock signals includes a shift register that generates first and second clock signals from an input clock signal. First and second circuit modules generate corresponding first and second interim signals using the first and second clock signals and first and second feedback signals, respectively. The first and second interim signals are non-overlapping by at least a predetermined minimum time difference. The first and second interim signals are multiplexed to generate an output signal. The output signal is delayed by a first predetermined time to generate a first delay signal. The first delay signal is delayed by a second predetermined time to generate a second delay signal. The second delay signal is de-multiplexed to generate the first and the second feedback signals, and the first delay signal is de-multiplexed to generate the set of multi-phase, non-overlapping clock signals.

Abstract translation: 用于产生多相不重叠时钟信号的电路包括从输入时钟信号产生第一和第二时钟信号的移位寄存器。 第一和第二电路模块分别使用第一和第二时钟信号以及第一和第二反馈信号产生对应的第一和第二中间信号。 第一和第二中间信号至少是预定的最小时间差不重叠。 第一和第二中间信号被多路复用以产生输出信号。 输出信号被延迟第一预定时间以产生第一延迟信号。 第一延迟信号被延迟第二预定时间以产生第二延迟信号。 第二延迟信号被解复用以产生第一和第二反馈信号，并且第一延迟信号被去多路复用以产生一组多相不重叠的时钟信号。

公开(公告)号：US20130187696A1

公开(公告)日：2013-07-25

申请号：US13356610

申请日：2012-01-23

Applicant: Siddhartha Gopal Krishna ,  Senthil Velan K

Inventor： Siddhartha Gopal Krishna ,  Senthil Velan K

IPC: H03K3/00

CPC classification number: H03K5/13

Abstract: A circuit for generating multi-phase, non-overlapping clock signals includes a shift register that generates first and second clock signals from an input clock signal. First and second circuit modules generate corresponding first and second interim signals using the first and second clock signals and first and second feedback signals, respectively. The first and second interim signals are non-overlapping by at least a predetermined minimum time difference. The first and second interim signals are multiplexed to generate an output signal. The output signal is delayed by a first predetermined time to generate a first delay signal. The first delay signal is delayed by a second predetermined time to generate a second delay signal. The second delay signal is de-multiplexed to generate the first and the second feedback signals, and the first delay signal is de-multiplexed to generate the set of multi-phase, non-overlapping clock signals.

Abstract translation: 用于产生多相不重叠时钟信号的电路包括从输入时钟信号产生第一和第二时钟信号的移位寄存器。 第一和第二电路模块分别使用第一和第二时钟信号以及第一和第二反馈信号产生对应的第一和第二中间信号。 第一和第二中间信号至少是预定的最小时间差不重叠。 第一和第二中间信号被多路复用以产生输出信号。 输出信号被延迟第一预定时间以产生第一延迟信号。 第一延迟信号被延迟第二预定时间以产生第二延迟信号。 第二延迟信号被解复用以产生第一和第二反馈信号，并且第一延迟信号被去多路复用以产生一组多相不重叠的时钟信号。