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公开(公告)号：US07714628B2
公开(公告)日：2010-05-11
申请号：US12059238
申请日：2008-03-31
IPC分类号： H03K3/356
CPC分类号： G11C7/02 , G11C11/4125
摘要： A flip-flop circuit is provided with an improved robustness to radiation induced soft errors. The flip-flop cell comprises the following elements. A transfer unit for receiving at least one data signal and at least one clock signal, a storage unit coupled to the transfer unit and a buffer unit coupled to the storage unit. The transfer unit includes a plurality of input nodes adapted to receive said at least one data signal and said at least one clock signal; a first output node for providing a sampled data signal in response to said at least one clock signal and said at least one data signal; and a second output node for providing a sampled inverse data signal, the sampled inverse data signal provided in response to said at least one clock signal and said at least one data signal. The storage unit comprises a first and a second storage nodes configured to receive and store the sampled data signal and the sampled inverse data signal. The storage unit comprises drive transistors configured to selectively couple one of the first and second storage nodes to ground; load transistors configured to selectively couple the other one of the first and second storage nodes to a power supply; and at least one stabilizer transistor configured to provide a corresponding redundant storage node and limit feedback between the first and second storage nodes, the redundant storage node being capable of restoring the first or second storage nodes in case of a soft error. The buffer unit provides an output sampled data signal as received from the storage unit.
摘要翻译： 触发器电路具有对辐射诱导的软错误的改进的鲁棒性。 触发器单元包括以下元件。 用于接收至少一个数据信号和至少一个时钟信号的传送单元，耦合到传送单元的存储单元和耦合到存储单元的缓冲单元。 传送单元包括适于接收所述至少一个数据信号和所述至少一个时钟信号的多个输入节点; 第一输出节点，用于响应于所述至少一个时钟信号和所述至少一个数据信号提供采样数据信号; 以及用于提供采样的反向数据信号的第二输出节点，响应于所述至少一个时钟信号和所述至少一个数据信号而提供的采样的反向数据信号。 存储单元包括被配置为接收和存储采样的数据信号和采样的反向数据信号的第一和第二存储节点。 存储单元包括被配置为选择性地将第一和第二存储节点之一耦合到地的驱动晶体管; 被配置为选择性地将第一和第二存储节点中的另一个耦合到电源的负载晶体管; 以及至少一个稳定器晶体管，被配置为提供对应的冗余存储节点并限制所述第一和第二存储节点之间的反馈，所述冗余存储节点在软错误的情况下能够恢复所述第一或第二存储节点。 缓冲单元提供从存储单元接收的输出采样数据信号。
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公开(公告)号：US20080180153A1
公开(公告)日：2008-07-31
申请号：US12059238
申请日：2008-03-31
IPC分类号： H03K3/356
CPC分类号： G11C7/02 , G11C11/4125
摘要： A flip-flop circuit is provided with an improved robustness to radiation induced soft errors. The flip-flop cell comprises the following elements. A transfer unit for receiving at least one data signal and at least one clock signal, a storage unit coupled to the transfer unit and a buffer unit coupled to the storage unit. The transfer unit includes a plurality of input nodes adapted to receive said at least one data signal and said at least one clock signal; a first output node for providing a sampled data signal in response to said at least one clock signal and said at least one data signal; and a second output node for providing a sampled inverse data signal, the sampled inverse data signal provided in response to said at least one clock signal and said at least one data signal. The storage unit comprises a first and a second storage nodes configured to receive and store the sampled data signal and the sampled inverse data signal. The storage unit comprises drive transistors configured to selectively couple one of the first and second storage nodes to ground; load transistors configured to selectively couple the other one of the first and second storage nodes to a power supply; and at least one stabilizer transistor configured to provide a corresponding redundant storage node and limit feedback between the first and second storage nodes, the redundant storage node being capable of restoring the first or second storage nodes in case of a soft error. The buffer unit provides an output sampled data signal as received from the storage unit.
摘要翻译： 触发器电路具有对辐射诱导的软错误的改进的鲁棒性。 触发器单元包括以下元件。 用于接收至少一个数据信号和至少一个时钟信号的传送单元，耦合到传送单元的存储单元和耦合到存储单元的缓冲单元。 传送单元包括适于接收所述至少一个数据信号和所述至少一个时钟信号的多个输入节点; 第一输出节点，用于响应于所述至少一个时钟信号和所述至少一个数据信号提供采样数据信号; 以及用于提供采样的反向数据信号的第二输出节点，响应于所述至少一个时钟信号和所述至少一个数据信号而提供的采样的反向数据信号。 存储单元包括被配置为接收和存储采样的数据信号和采样的反向数据信号的第一和第二存储节点。 存储单元包括被配置为选择性地将第一和第二存储节点之一耦合到地的驱动晶体管; 被配置为选择性地将第一和第二存储节点中的另一个耦合到电源的负载晶体管; 以及至少一个稳定器晶体管，被配置为提供对应的冗余存储节点并限制所述第一和第二存储节点之间的反馈，所述冗余存储节点在软错误的情况下能够恢复所述第一或第二存储节点。 缓冲单元提供从存储单元接收的输出采样数据信号。
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3.发明申请公开(公告)号：US20090316505A1
公开(公告)日：2009-12-24
申请号：US12549757
申请日：2009-08-28
CPC分类号： G11C7/02 , G11C11/4125
摘要： A Static Random Access Memory (SRAM) cell storage configuration is provided with an improved robustness to radiation induced soft errors. The SRAM cell storage configuration comprises the following elements. First and second storage nodes are configured to store complementary voltages. Drive transistors are configured to selectively couple one of the first and second storage nodes to ground. Load transistors are configured to selectively couple the other one of the first and second storage nodes to a power supply. At least one stabilizer transistor is configured to provide a corresponding redundant storage node and limit feedback between the first and second storage nodes, the redundant storage node being capable of restoring the first or second storage nodes in case of a soft error.
摘要翻译： 静态随机存取存储器（SRAM）单元存储配置具有改善的对辐射诱导的软错误的鲁棒性。 SRAM单元存储配置包括以下元件。 配置第一和第二存储节点以存储互补电压。 驱动晶体管被配置为选择性地将第一和第二存储节点之一耦合到地。 负载晶体管被配置为选择性地将第一和第二存储节点中的另一个耦合到电源。 至少一个稳定器晶体管被配置为提供对应的冗余存储节点并限制第一和第二存储节点之间的反馈，冗余存储节点在软错误的情况下能够恢复第一或第二存储节点。
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公开(公告)号：US07613067B2
公开(公告)日：2009-11-03
申请号：US11876223
申请日：2007-10-22
申请人： Manoj Sachdev , Shah M Jahinuzzaman
发明人： Manoj Sachdev , Shah M Jahinuzzaman
IPC分类号： G11C8/00
CPC分类号： G11C7/02 , G11C11/4125
摘要： A Static Random Access Memory (SRAM) cell is provided with an improved robustness to radiation induced soft errors. The SRAM cell includes the following elements. First and second storage nodes are configured to store complementary voltages. Access transistors are configured to selectively couple the first and second storage nodes to a corresponding bit line. Drive transistors are configured to selectively couple one of the first and second storage nodes to ground. Load transistors are configured to selectively couple the other one of the first and second storage nodes to a power supply. At least one stabilizer transistor is configured to provide a corresponding redundant storage node and limit feedback between the first and second storage nodes. The redundant storage node is capable of restoring the first or second storage nodes in case of a soft error.
摘要翻译： 静态随机存取存储器（SRAM）单元具有改善的对辐射诱导的软错误的鲁棒性。 SRAM单元包括以下元件。 配置第一和第二存储节点以存储互补电压。 接入晶体管被配置为选择性地将第一和第二存储节点耦合到对应的位线。 驱动晶体管被配置为选择性地将第一和第二存储节点之一耦合到地。 负载晶体管被配置为选择性地将第一和第二存储节点中的另一个耦合到电源。 至少一个稳定器晶体管被配置为提供对应的冗余存储节点并限制第一和第二存储节点之间的反馈。 冗余存储节点在软错误的情况下能够恢复第一或第二存储节点。
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公开(公告)号：US20170093380A1
公开(公告)日：2017-03-30
申请号：US14866469
申请日：2015-09-25
IPC分类号： H03K3/356
CPC分类号： H03K3/356104 , H03K3/0375
摘要： An apparatus is described having a latch circuit. The latch circuit includes redundant data inputs, redundant data outputs, redundant clock inputs and circuitry to self-correct a soft-error.
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6.发明授权公开(公告)号：US07872938B2
公开(公告)日：2011-01-18
申请号：US12549757
申请日：2009-08-28
申请人： Manoj Sachdev , Shah M Jahinuzzaman
发明人： Manoj Sachdev , Shah M Jahinuzzaman
IPC分类号： G11C8/00
CPC分类号： G11C7/02 , G11C11/4125
摘要： A Static Random Access Memory (SRAM) cell storage configuration is described, having an improved robustness to radiation induced soft errors. The SRAM cell storage configuration comprises the following elements. First and second storage nodes are configured to store complementary voltages. Drive transistors are configured to selectively couple one of the first and second storage nodes to ground. Load transistors are configured to selectively couple the other one of the first and second storage nodes to a power supply. At least one stabilizer transistor is configured to provide a corresponding redundant storage node and limit feedback between the first and second storage nodes, the redundant storage node being capable of restoring the first or second storage nodes in case of a soft error.
摘要翻译： 描述了静态随机存取存储器（SRAM）单元存储配置，其对辐射诱导的软错误具有改进的鲁棒性。 SRAM单元存储配置包括以下元件。 配置第一和第二存储节点以存储互补电压。 驱动晶体管被配置为选择性地将第一和第二存储节点之一耦合到地。 负载晶体管被配置为选择性地将第一和第二存储节点中的另一个耦合到电源。 至少一个稳定器晶体管被配置为提供对应的冗余存储节点并限制第一和第二存储节点之间的反馈，冗余存储节点在软错误的情况下能够恢复第一或第二存储节点。
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