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公开(公告)号：US08464202B2
公开(公告)日：2013-06-11
申请号：US13114834
申请日：2011-05-24
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5063 , G06F2217/66
摘要： A parameterizable design system is for use with semiconductor analog circuits and includes an interface unit connected to provide access to the system, a database unit connected to supply a library of parameterizable analog building blocks for a design entity, and a parameterization unit connected to select a parameter for one of the library of parameterizable analog building blocks to meet a design specification of the design entity. Additionally, the parameterizable design system may also include a simulation unit connected to simulate an operation of the design entity employing the parameter, and an analyzer unit connected to analyze a sensitivity of the parameter for the design entity based on the design specification. A method of designing a semiconductor analog circuit is also included.
摘要翻译： 可参数化的设计系统与半导体模拟电路一起使用，并且包括被连接以提供对系统的访问的接口单元，连接到用于为设计实体提供可参数化的模拟构建块的库的数据库单元，以及连接以选择一个 参数为可参数化的模拟构建块之一，以满足设计实体的设计规范。 此外，可参数化设计系统还可以包括连接以模拟使用参数的设计实体的操作的模拟单元，以及连接以基于设计规范分析设计实体的参数的灵敏度的分析器单元。 还包括设计半导体模拟电路的方法。
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公开(公告)号：US20120304140A1
公开(公告)日：2012-11-29
申请号：US13114834
申请日：2011-05-24
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5063 , G06F2217/66
摘要： A parameterizable design system is for use with semiconductor analog circuits and includes an interface unit connected to provide access to the system, a database unit connected to supply a library of parameterizable analog building blocks for a design entity, and a parameterization unit connected to select a parameter for one of the library of parameterizable analog building blocks to meet a design specification of the design entity. Additionally, the parameterizable design system may also include a simulation unit connected to simulate an operation of the design entity employing the parameter, and an analyzer unit connected to analyze a sensitivity of the parameter for the design entity based on the design specification. A method of designing a semiconductor analog circuit is also included.
摘要翻译： 可参数化的设计系统与半导体模拟电路一起使用，并且包括被连接以提供对系统的访问的接口单元，连接到用于为设计实体提供可参数化的模拟构建块的库的数据库单元，以及连接以选择一个 参数为可参数化的模拟构建块之一，以满足设计实体的设计规范。 此外，可参数化设计系统还可以包括连接以模拟使用参数的设计实体的操作的模拟单元，以及连接以基于设计规范分析设计实体的参数的灵敏度的分析器单元。 还包括设计半导体模拟电路的方法。
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公开(公告)号：US20130298090A1
公开(公告)日：2013-11-07
申请号：US13462539
申请日：2012-05-02
申请人： Joseph A. Gmitter , Shawn Boshart
发明人： Joseph A. Gmitter , Shawn Boshart
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/82
摘要： The invention may be embodied in a network resistor model analysis tool for an Electrical Rule Checking (ERC) system. The network resistor model analysis tool typically includes, but need not be limited to, (i) a recursive, deterministic resistor path algorithm that identifies all valid resistor paths from a start net to a stopping net in a netlist corresponding to an analog circuit, (ii) a programming representation algorithm complete for representing the resistor paths in a programmatic format accessible through an application program interface, and (iii) a recursive, deterministic resistance value algorithm that solves the programmatically represented network to determine a total resistance value for each valid path and each resistor leg in each valid path.
摘要翻译： 本发明可以体现在用于电气规则检查（ERC）系统的网络电阻模型分析工具中。 网络电阻器模型分析工具通常包括但不限于（i）递归确定性电阻器路径算法，其识别从对应于模拟电路的网表中的起始网到停止网的所有有效电阻器路径（ ii）完整的编程表示算法，用于以可通过应用程序接口访问的编程格式表示电阻器路径，以及（iii）递归的确定性电阻值算法，其解决了以编程方式表示的网络，以确定每个有效路径的总电阻值 并且每个有效路径中的每个电阻器支路。
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4.发明授权Integrated computer-aided circuit design kit facilitating verification of designs across different process technologies 失效集成的计算机辅助电路设计工具，便于不同工艺技术的设计验证公开(公告)号：US07340697B2
公开(公告)日：2008-03-04
申请号：US11019885
申请日：2004-12-22
CPC分类号： G06F17/505 , G06F17/5036
摘要： Methods and apparatus are described that allow an integrated circuit designer to design integrated circuits for more than one process technology using a single master design environment. The master design environment is achieved, in part, by the creation of a centralized master database that comprises device models belonging to more than one process technology. Creation of the master database occurs by parsing a plurality of external databases comprising device models belonging to more than one process technology. The use of a single master design environment simplifies the task of designing an integrated circuit, and also reduces the chance of error.
摘要翻译： 描述了允许集成电路设计者使用单个主设计环境为多于一个工艺技术设计集成电路的方法和装置。 主设计环境部分地通过创建一个集成的主数据库来实现，该主数据库包含属于多个进程技术的设备模型。 主数据库的创建通过解析包含属于多于一种处理技术的设备模型的多个外部数据库而发生。 使用单个主设计环境简化了设计集成电路的任务，并且还减少了错误的几率。
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5.发明申请Integrated computer-aided circuit design kit facilitating verification of designs across different process technologies 失效集成的计算机辅助电路设计工具，便于不同工艺技术的设计验证公开(公告)号：US20060136860A1
公开(公告)日：2006-06-22
申请号：US11019885
申请日：2004-12-22
申请人： Shawn Boshart , Jee-Hoon Krska , John Lentz , Joshua Williams
发明人： Shawn Boshart , Jee-Hoon Krska , John Lentz , Joshua Williams
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5036
摘要： Methods and apparatus are described that allow an integrated circuit designer to design integrated circuits for more than one process technology using a single master design environment. The master design environment is achieved, in part, by the creation of a centralized master database that comprises device models belonging to more than one process technology. Creation of the master database occurs by parsing a plurality of external databases comprising device models belonging to more than one process technology. The use of a single master design environment simplifies the task of designing an integrated circuit, and also reduces the chance of error.
摘要翻译： 描述了允许集成电路设计者使用单个主设计环境为多于一个工艺技术设计集成电路的方法和装置。 主设计环境部分地通过创建一个集成的主数据库来实现，该主数据库包含属于多个进程技术的设备模型。 主数据库的创建通过解析包含属于多于一种处理技术的设备模型的多个外部数据库而发生。 使用单个主设计环境简化了设计集成电路的任务，并且还减少了错误的几率。
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