CLOCK JITTER MEASUREMENT CIRCUIT AND INTEGRATED CIRCUIT HAVING THE SAME
    1.
    发明申请
    CLOCK JITTER MEASUREMENT CIRCUIT AND INTEGRATED CIRCUIT HAVING THE SAME 有权
    时钟抖动测量电路和集成电路

    公开(公告)号:US20090271133A1

    公开(公告)日:2009-10-29

    申请号:US12108796

    申请日:2008-04-24

    CPC classification number: G01R29/26 G01R31/3016 G01R31/31709

    Abstract: Provided is a measurement circuit for measuring a jitter of a clock signal. Delay elements delay the clock signal into delayed clock signal. Latches latch the delayed clock signals to indicate whether transition edges of the clock signal is within a window value which is corresponding to delays of the delay elements. Based on the latch result from the latches, a finite state machine generates control signals for controlling the delay elements. If the latch result indicates that the transition edges of the clock signal is not within the window value, the control signals adjust the delays of the delay elements and the window value. The jitter of the clock signal is measured based on the delays of the delay elements and the window value.

    Abstract translation: 提供了一种用于测量时钟信号的抖动的测量电路。 延迟元件将时钟信号延迟到延迟的时钟信号。 锁存器锁存延迟的时钟信号以指示时钟信号的转换边沿是否在对应于延迟元件的延迟的窗口值内。 基于锁存器的锁存结果,有限状态机产生用于控制延迟元件的控制信号。 如果锁存结果指示时钟信号的转换边缘不在窗口值内,则控制信号调整延迟元件的延迟和窗口值。 基于延迟元件的延迟和窗口值来测量时钟信号的抖动。

    Clock jitter measurement circuit and integrated circuit having the same
    2.
    发明授权
    Clock jitter measurement circuit and integrated circuit having the same 有权
    时钟抖动测量电路和集成电路相同

    公开(公告)号:US07945404B2

    公开(公告)日:2011-05-17

    申请号:US12108796

    申请日:2008-04-24

    CPC classification number: G01R29/26 G01R31/3016 G01R31/31709

    Abstract: Provided is a measurement circuit for measuring a jitter of a clock signal. Delay elements delay the clock signal into delayed clock signal. Latches latch the delayed clock signals to indicate whether transition edges of the clock signal is within a window value which is corresponding to delays of the delay elements. Based on the latch result from the latches, a finite state machine generates control signals for controlling the delay elements. If the latch result indicates that the transition edges of the clock signal is not within the window value, the control signals adjust the delays of the delay elements and the window value. The jitter of the clock signal is measured based on the delays of the delay elements and the window value.

    Abstract translation: 提供了一种用于测量时钟信号的抖动的测量电路。 延迟元件将时钟信号延迟到延迟的时钟信号。 锁存器锁存延迟的时钟信号以指示时钟信号的转换边沿是否在对应于延迟元件的延迟的窗口值内。 基于锁存器的锁存结果,有限状态机产生用于控制延迟元件的控制信号。 如果锁存结果指示时钟信号的转换边缘不在窗口值内,则控制信号调整延迟元件的延迟和窗口值。 基于延迟元件的延迟和窗口值来测量时钟信号的抖动。

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