公开(公告)号：US20090125576A1

公开(公告)日：2009-05-14

申请号：US11979964

申请日：2007-11-13

Applicant: Shiann Shiun Jeng ,  Hsing Chen Lin ,  Wei Li Tou ,  Pao Kuei Horng

Inventor： Shiann Shiun Jeng ,  Hsing Chen Lin ,  Wei Li Tou ,  Pao Kuei Horng

IPC: G06F7/52

CPC classification number: G06F7/68

Abstract: This invention relates to Pade approximation convert circuit of the direct digital frequency synthesizer in which a multiplier receives and multiplies a first input signal and a variable signal so as to produce a multiplication signal; a divider receives and divides a second input signal and a variable signal so as to produce a division signal; an adder receives and adds the multiplication signal and the division signal so as to generate an output signal, that is then returned back to the divider. A quarter period of a sinusoidal wave signal is completed by the proceeding of direct calculation two times such that the time for the calculation of a complete sinusoidal wave can be saved and the area of the calculation circuit can be reduced.

Abstract translation: 本发明涉及直接数字频率合成器的Pade近似转换电路，其中乘法器接收并乘以第一输入信号和可变信号以产生乘法信号; 分频器接收并分割第二输入信号和可变信号，以产生除法信号; 加法器接收并相加乘法信号和除法信号，以产生输出信号，然后将其返回分频器。 通过直接计算两次完成正弦波信号的四分之一周期，使得可以节省计算完整正弦波的时间，并且可以减少计算电路的面积。

公开(公告)号：US08060547B2

公开(公告)日：2011-11-15

申请号：US11979964

申请日：2007-11-13

Applicant: Shiann Shiun Jeng ,  Hsing Chen Lin ,  Wei Li Tou ,  Pao Kuei Horng

Inventor： Shiann Shiun Jeng ,  Hsing Chen Lin ,  Wei Li Tou ,  Pao Kuei Horng

IPC: G06F1/02

CPC classification number: G06F7/68

Abstract: This invention relates to Pade approximation convert circuit of the direct digital frequency synthesizer in which a multiplier receives and multiplies a first input signal and a variable signal so as to produce a multiplication signal; a divider receives and divides a second input signal and a variable signal so as to produce a division signal; an adder receives and adds the multiplication signal and the division signal so as to generate an output signal, that is then returned back to the divider. A quarter period of a sinusoidal wave signal is completed by the proceeding of direct calculation two times such that the time for the calculation of a complete sinusoidal wave can be saved and the area of the calculation circuit can be reduced.

Abstract translation: 本发明涉及直接数字频率合成器的Pade近似转换电路，其中乘法器接收并乘以第一输入信号和可变信号以产生乘法信号; 分频器接收并分割第二输入信号和可变信号，以产生除法信号; 加法器接收并相加乘法信号和除法信号，以产生输出信号，然后将其返回分频器。 通过直接计算两次完成正弦波信号的四分之一周期，使得可以节省计算完整正弦波的时间，并且可以减少计算电路的面积。

公开(公告)号：US20070155192A1

公开(公告)日：2007-07-05

申请号：US11546294

申请日：2006-10-12

Applicant: Shiann Shiun Jeng ,  Chen Wan Tsung ,  Yung Tzu Ting ,  Syue Ju Syue

Inventor： Shiann Shiun Jeng ,  Chen Wan Tsung ,  Yung Tzu Ting ,  Syue Ju Syue

IPC: H01R39/00

CPC classification number: G01S3/74 ,  H04B7/086

Abstract: A module and a method for estimating signal direction of arrival are disclosed. The module consists of a processing unit and a direction finder. Using spatial signatures at different carrier frequencies, the processing unit generates a generating set of a subspace. Based on the generating set, the signal subspace is extended. Then, the direction finder estimates signal direction of arrival according to the signal subspace. The module for estimating signal direction of arrival of the present invention effectively reduces wrong estimation of the signal direction of arrival caused by loss of rank.

Abstract translation: 公开了一种用于估计信号到达方向的模块和方法。 该模块由处理单元和取向器组成。 使用不同载波频率的空间特征，处理单元生成子空间的生成集合。 基于生成集，信号子空间被扩展。 然后，取向器根据信号子空间估计信号到达方向。 用于估计本发明的信号到达方向的模块有效地减少了由于秩丢失引起的信号到达方向的错误估计。