公开(公告)号：US5416746A

公开(公告)日：1995-05-16

申请号：US974222

申请日：1992-11-10

申请人： Yasunori Sato ,  Shosaku Tsukagoshi ,  Yoshio Sakata

发明人： Yasunori Sato ,  Shosaku Tsukagoshi ,  Yoshio Sakata

IPC分类号： G11C11/41 ,  G11C7/00 ,  G11C8/00

CPC分类号： G11C7/00

摘要： A memory circuit includes an input selector for receiving input data serially at an interval of a period T and outputting the input data and an address counter for generating first address data sequentially at an interval of a having period 2T and second address data sequentially at an interval having period 2T. The second address data is delayed a period T from the first address data. The memory circuit of the present invention further includes two memory blocks coupled to the input selector and address counter. One memory block stores even numbered input data in response to the first address data and outputs them at the interval of the period 2T. The other memory block stores odd numbered input data in response to the second address data and outputs them at the interval of the period 2T.

摘要翻译： 存储电路包括：输入选择器，用于以周期T的间隔串行接收输入数据，并输出输入数据;以及地址计数器，用于以具有周期2T的间隔依次产生第一地址数据，第二地址数据以间隔顺序 有2T。 第二地址数据从第一地址数据延迟周期T. 本发明的存储电路还包括耦合到输入选择器和地址计数器的两个存储块。 一个存储器块响应于第一地址数据存储偶数编号的输入数据，并以周期2T的间隔输出它们。 其他存储器块响应于第二地址数据存储奇数编号的输入数据，并以周期2T的间隔输出它们。