公开(公告)号：US6054359A

公开(公告)日：2000-04-25

申请号：US332426

申请日：1999-06-14

申请人： Yu-Ming Tsui ,  Wen-Cheng Chang ,  Shung-Jen Yu ,  Sheng-Yih Ting

发明人： Yu-Ming Tsui ,  Wen-Cheng Chang ,  Shung-Jen Yu ,  Sheng-Yih Ting

IPC分类号： H01L21/02 ,  H01L27/06 ,  H01L21/8244

CPC分类号： H01L28/20 ,  H01L27/0629

摘要： A high-sheet-resistance polysilicon resistor for integrated circuits is achieved by using a two-layer polysilicon process. After forming FET gate electrodes and capacitor bottom electrodes from a polycide layer, a thin interpolysilicon oxide (IPO) layer is deposited to form the capacitor interelectrode dielectric. A doped polysilicon layer and an undoped polysilicon layer are deposited and patterned to form the resistor. The doped polysilicon layer is in-situ doped to minimize the temperature and voltage coefficients of resistivity. Since the undoped polysilicon layer has a very high resistance (infinite), the resistance is predominantly determined by the doped polysilicon layer. The doped polysilicon layer can be reduced in thickness (less than 1000 Angstroms) to further increase the sheet resistance for mixed-mode circuits, while the undoped polysilicon layer allows contact openings to be etched in an insulating layer over the resistor without overetching the thin doped polysilicon layer and damaging the underlying IPO layer.

摘要翻译： 用于集成电路的高电阻多晶硅电阻器通过使用两层多晶硅工艺实现。 在从多晶硅层形成FET栅电极和电容器底电极之后，沉积薄的多晶硅氧化物（IPO）层以形成电容器电极间电介质。 沉积掺杂多晶硅层和未掺杂多晶硅层并构图以形成电阻器。 掺杂多晶硅层被原位掺杂以最小化电阻率的温度和电压系数。 由于未掺杂的多晶硅层具有非常高的电阻（无限大），所以电阻主要由掺杂多晶硅层决定。 掺杂多晶硅层可以减小厚度（小于1000埃），以进一步提高混合模式电路的薄层电阻，而未掺杂的多晶硅层允许在电阻器上的绝缘层中蚀刻接触开口，而不会过滤掉掺杂 多晶硅层，并损坏底层的IPO层。

公开(公告)号：US06313516B1

公开(公告)日：2001-11-06

申请号：US09524523

申请日：2000-03-13

申请人： Yu-Ming Tsui ,  Wen-Cheng Chang ,  Shung-Jen Yu

发明人： Yu-Ming Tsui ,  Wen-Cheng Chang ,  Shung-Jen Yu

IPC分类号： H01L2900

CPC分类号： H01L28/20 ,  H01L27/0629

摘要： A high-sheet-resistance polysilicon resistor for integrated circuits is achieved by using a two-layer polysilicon process. After forming FET gate electrodes and capacitor bottom electrodes from a polycide layer, a thin interpolysilicon oxide (IPO) layer is deposited to form the capacitor interelectrode dielectric. A doped polysilicon layer and an undoped polysilicon layer are deposited and patterned to form the resistor. The doped polysilicon layer is in-situ doped to minimize the temperature and voltage coefficients of resistivity. Since the undoped polysilicon layer has a very high resistance (infinite), the resistance is predominantly determined by the doped polysilicon layer. The doped polysilicon layer can be reduced in thickness (less than 1000 Angstroms) to further increase the sheet resistance for mixed-mode circuits, while the undoped polysilicon layer allows contact openings to be etched in an insulating layer over the resistor without overetching the thin doped polysilicon layer and damaging the underlying IPO layer.

摘要翻译： 用于集成电路的高电阻多晶硅电阻器通过使用两层多晶硅工艺实现。 在从多晶硅层形成FET栅电极和电容器底电极之后，沉积薄的多晶硅氧化物（IPO）层以形成电容器电极间电介质。 沉积掺杂多晶硅层和未掺杂多晶硅层并构图以形成电阻器。 掺杂多晶硅层被原位掺杂以最小化电阻率的温度和电压系数。 由于未掺杂的多晶硅层具有非常高的电阻（无限大），所以电阻主要由掺杂多晶硅层决定。 掺杂多晶硅层可以减小厚度（小于1000埃），以进一步提高混合模式电路的薄层电阻，而未掺杂的多晶硅层允许在电阻器上的绝缘层中蚀刻接触开口，而不会过滤掉掺杂 多晶硅层，并损坏底层的IPO层。