公开(公告)号：US5471095A

公开(公告)日：1995-11-28

申请号：US237309

申请日：1994-05-03

申请人： Isamu Kaminaga ,  Shuuichi Matsue ,  Takahiko Arakawa ,  Shuuichi Katoh ,  Masahiro Ueda

发明人： Isamu Kaminaga ,  Shuuichi Matsue ,  Takahiko Arakawa ,  Shuuichi Katoh ,  Masahiro Ueda

IPC分类号： H01L21/3205 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/48 ,  H01L29/62

CPC分类号： H01L23/5222 ,  H01L23/5283 ,  H01L2924/0002

摘要： There is disclosed a semiconductor integrated circuit device including an element-to-element line (10A) of a quadrangular (rectangular) configuration in cross section having horizontal upper and lower surfaces, with its lower surface corners on the side of a semiconductor substrate (1) chamfered on the slant. This increases the horizontal distance between adjacent lines and decreases the height of the line, permitting the adjacent line-to-line parasitic capacitance to be lower than that of the prior art line of a quadrangular configuration in cross section under the same height and line-to-line horizontal distance conditions. The line-to-substrate parasitic capacitance is also permitted to be lower for similar reasons. The semiconductor integrated circuit device is thus provided in which the parasitic capacitances generated by forming lines are minimized.

摘要翻译： 公开了一种半导体集成电路器件，其包括具有水平上表面和下表面的横截面的四边形（矩形）构造的元件间元件线（10A），其下表面拐角位于半导体衬底（1） ）在斜面上倒角。 这增加了相邻线之间的水平距离并且降低了线的高度，允许相邻的线对线寄生电容低于在相同高度和线宽处的横截面中的四边形配置的现有技术线的相邻线对线寄生电容， 线间水平距离条件。 由于类似的原因，线对衬底寄生电容也被允许更低。 因此，提供了通过形成线产生的寄生电容最小化的半导体集成电路器件。