公开(公告)号：US20240311156A1

公开(公告)日：2024-09-19

申请号：US18237511

申请日：2023-08-24

申请人： Simplex Micro, Inc.

发明人： Thang Minh Tran

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3836 ,  G06F9/30043 ,  G06F9/3016

摘要： A processor includes a time counter and a time-resource matrix and provides a method for statically dispatching load/store instructions if the required resources are available based on data stored in the time-resource matrix, and wherein execution times for the load/store instructions use a time count from the time counter to specify when the load/store instructions may be provided to a load-store unit pipeline. The execution times of the load instruction is based on the data cache hit latency time. A delay of the load/store instruction causes the load/store instruction to be replayed with known or estimated time. A load-store unit employs multiple bank queues to access multiple data banks of a data cache.

公开(公告)号：US20240020122A1

公开(公告)日：2024-01-18

申请号：US18135481

申请日：2023-04-17

申请人： Simplex Micro, Inc.

发明人： Thang Minh Tran

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/30065 ,  G06F9/3836

摘要： A processor includes a loop detection unit to detect a phantom-loop based on the resources reserved for execution of the phantom loop. The processor executes the phantom loop by reading source operand data on a first iteration of the loop and writing back data on the last iteration of the loop while allowing instructions after the loop to be concurrently executed.

公开(公告)号：US20230350679A1

公开(公告)日：2023-11-02

申请号：US17733689

申请日：2022-04-29

申请人： Simplex Micro, Inc.

发明人： Thang Minh Tran

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/3012 ,  G06F9/30145 ,  G06F9/384 ,  G06F9/3885 ,  G06F9/30036

摘要： A processor includes a plurality of register sets of a register file, and a plurality sets of functional units which are coupled by sets of dedicated read and write buses to allow parallel execution of instruction. The register sets and functional units are organized as odd and even sets. Shared buses may also be employed. The processor may also include a time counter and a time-resource matrix and provides a method for statically dispatching instructions.

公开(公告)号：US20230342148A1

公开(公告)日：2023-10-26

申请号：US17725342

申请日：2022-04-20

申请人： Simplex Micro, Inc.

发明人： David Witt ,  Thang Minh Tran

IPC分类号： G06F9/30 ,  G06F12/0811

CPC分类号： G06F9/30043 ,  G06F12/0811 ,  G06F9/30145 ,  G06F9/3005 ,  G06F9/3012 ,  G06F2212/1024

摘要： A processor includes an instruction issue unit that receives a first instruction, and issues the first instruction with a write time, which for a load instruction corresponds to a data cache latency time or to a non-cacheable latency time of a non-cacheable predictor. The non-cacheable predictor includes a tag array and data array with a plurality of entries to predict non-cacheable latency times of non-cacheable load instructions. The non-cacheable predictor can be implemented as a direct map, an N-way associative cache, or a fully associative cache.

公开(公告)号：US20230244493A1

公开(公告)日：2023-08-03

申请号：US17672622

申请日：2022-02-15

申请人： Simplex Micro, Inc.

发明人： Thang Minh Tran

IPC分类号： G06F9/38 ,  G06F1/12

CPC分类号： G06F9/3838 ,  G06F9/3848 ,  G06F1/12

摘要： A processor includes a time counter and a register scoreboard and operates to statically dispatch instructions with preset execution times based on a write time of a register in the register scoreboard and a time count of the time counter provided to an execution pipeline.

公开(公告)号：US20230244491A1

公开(公告)日：2023-08-03

申请号：US17697870

申请日：2022-03-17

申请人： Simplex Micro, Inc.

发明人： Thang Minh Tran

IPC分类号： G06F9/38 ,  G06F1/14

CPC分类号： G06F9/3836 ,  G06F1/14

摘要： A multithread processor includes a time counter and a register scoreboard and provides a method for statically dispatching instructions with preset execution times based on a write time of a register in the register scoreboard and the time counter provided to an execution pipeline.

公开(公告)号：US20230393852A1

公开(公告)日：2023-12-07

申请号：US17829909

申请日：2022-06-01

申请人： Simplex Micro, Inc.

发明人： Thang Minh Tran

IPC分类号： G06F9/38 ,  G06F1/10 ,  G06F9/30

CPC分类号： G06F9/3836 ,  G06F1/10 ,  G06F9/30036

摘要： A processor includes a time counter and a vector coprocessor for executing vector instructions and providing a method for statically dispatching vector instructions with preset execution times based on a write time of a register in a coprocessor register scoreboard and a time counter provided to a vector execution pipeline.

公开(公告)号：US20230350680A1

公开(公告)日：2023-11-02

申请号：US17733728

申请日：2022-04-29

申请人： Simplex Micro, Inc.

发明人： Thang Minh Tran

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/3012 ,  G06F9/384 ,  G06F9/30145 ,  G06F9/3885

摘要： A processor includes a time counter and a time-resource matrix and statically dispatches baseline and extended instructions. The processor includes a plurality of register sets of a register file and a plurality of sets of functional units which are coupled by sets of dedicated read and write buses to allow parallel execution of baseline and extended instructions.

公开(公告)号：US12106114B2

公开(公告)日：2024-10-01

申请号：US17733728

申请日：2022-04-29

申请人： Simplex Micro, Inc.

发明人： Thang Minh Tran

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3885 ,  G06F9/3012

摘要： A processor includes a time counter and a time-resource matrix and statically dispatches baseline and extended instructions. The processor includes a plurality of register sets of a register file and a plurality of sets of functional units which are coupled by sets of dedicated read and write buses to allow parallel execution of baseline and extended instructions.

公开(公告)号：US11954491B2

公开(公告)日：2024-04-09

申请号：US17697870

申请日：2022-03-17

申请人： Simplex Micro, Inc.

发明人： Thang Minh Tran

IPC分类号： G06F9/38 ,  G06F1/14

CPC分类号： G06F9/3836 ,  G06F1/14

摘要： A multithread processor includes a time counter and a register scoreboard and provides a method for statically dispatching instructions with preset execution times based on a write time of a register in the register scoreboard and the time counter provided to an execution pipeline.