公开(公告)号：US08455309B2

公开(公告)日：2013-06-04

申请号：US13347361

申请日：2012-01-10

申请人： Song-Ju Lee ,  Jeong Soo Park ,  Byung-Gook Park ,  Hyun Woo Kim

发明人： Song-Ju Lee ,  Jeong Soo Park ,  Byung-Gook Park ,  Hyun Woo Kim

IPC分类号： H01L33/08

CPC分类号： H01L29/66356 ,  H01L29/7391

摘要： A technology is capable of simplifying a process of manufacturing an asymmetric device in forming a Tunneling Field Effect Transistor (TFET) structure. A method for manufacturing a semiconductor device comprises forming a conductive pattern over a semiconductor substrate, implanting impurity ions with the conductive pattern as a mask to form a first junction region in the semiconductor substrate, forming a first insulating film planarized with the conductive pattern over the first junction region, etching the top of the conductive pattern to expose a sidewall of the first insulating film, forming a spacer at the sidewall of the first insulating film disposed over the conductive pattern, etching the conductive pattern with the spacer as an etching mask to form a gate pattern, and forming a second junction region in the semiconductor substrate with the gate pattern as a mask.

摘要翻译： 一种技术能够简化在形成隧道场效应晶体管（TFET）结构中制造非对称器件的工艺。 一种制造半导体器件的方法，包括在半导体衬底上形成导电图案，将导电图案作为掩模注入杂质离子，以在半导体衬底中形成第一结区，在导电图案上形成平坦化的第一绝缘膜， 第一接合区域，蚀刻导电图案的顶部以暴露第一绝缘膜的侧壁，在布置在导电图案上的第一绝缘膜的侧壁处形成间隔物，用间隔物蚀刻导电图案作为蚀刻掩模， 形成栅极图案，并且以栅极图案作为掩模在半导体衬底中形成第二结区域。

公开(公告)号：US20130102114A1

公开(公告)日：2013-04-25

申请号：US13347361

申请日：2012-01-10

申请人： Song-Ju LEE ,  Jeong Soo Park ,  Byung-Gook Park ,  Hyun Woo Kim

发明人： Song-Ju LEE ,  Jeong Soo Park ,  Byung-Gook Park ,  Hyun Woo Kim

IPC分类号： H01L21/336

CPC分类号： H01L29/66356 ,  H01L29/7391

摘要： A technology is capable of simplifying a process of manufacturing an asymmetric device in forming a Tunneling Field Effect Transistor (TFET) structure. A method for manufacturing a semiconductor device comprises forming a conductive pattern over a semiconductor substrate, implanting impurity ions with the conductive pattern as a mask to form a first junction region in the semiconductor substrate, forming a first insulating film planarized with the conductive pattern over the first junction region, etching the top of the conductive pattern to expose a sidewall of the first insulating film, forming a spacer at the sidewall of the first insulating film disposed over the conductive pattern, etching the conductive pattern with the spacer as an etching mask to form a gate pattern, and forming a second junction region in the semiconductor substrate with the gate pattern as a mask.

摘要翻译： 一种技术能够简化在形成隧道场效应晶体管（TFET）结构中制造非对称器件的工艺。 一种制造半导体器件的方法，包括在半导体衬底上形成导电图案，将导电图案作为掩模注入杂质离子，以在半导体衬底中形成第一结区，在导电图案上形成平坦化的第一绝缘膜， 第一接合区域，蚀刻导电图案的顶部以暴露第一绝缘膜的侧壁，在布置在导电图案上的第一绝缘膜的侧壁处形成间隔物，用间隔物蚀刻导电图案作为蚀刻掩模， 形成栅极图案，并且以栅极图案作为掩模在半导体衬底中形成第二结区域。