公开(公告)号：US06411280B1

公开(公告)日：2002-06-25

申请号：US09362232

申请日：1999-07-28

Applicant: Jan W. Aarts ,  Marc E. C Lambrechts ,  Stefaan M. M. Note

Inventor： Jan W. Aarts ,  Marc E. C Lambrechts ,  Stefaan M. M. Note

IPC: G09G508

CPC classification number: A63F13/285 ,  A63F13/06 ,  A63F2300/1037 ,  G06F3/011 ,  G06F3/016 ,  G06F3/03543 ,  G06F2203/013

Abstract: An input device (200) comprises a number of distinct touch areas (230, 232), i.e. areas which are normally in contact with a user while manipulating the device. At least two of such touch areas (230, 232) have corresponding tactual cue generating units (240, 242) for conveying tactual cues via the touch areas (230, 232) to the user. In an application in which the input device (200) is used, the tactual cues can convey location or direction information relating to the application, by independently operating the tactual cue generating units (240, 242).

Abstract translation: 输入设备（200）包括多个不同的触摸区域（230,232），即在操纵设备时通常与用户接触的区域。 这种触摸区域（230,232）中的至少两个具有用于经由触摸区域（230,232）向用户传送触觉提示的相应的触觉提示产生单元（240,242）。 在使用输入装置（200）的应用中，触发线索可以通过独立地操作触发提示产生单元（240,242）来传送与应用有关的位置或方向信息。

公开(公告)号：US06122751A

公开(公告)日：2000-09-19

申请号：US798196

申请日：1996-12-09

Applicant: Mark A. E. Janssens ,  Stefaan M. M. Note

Inventor： Mark A. E. Janssens ,  Stefaan M. M. Note

IPC: H03K5/00 ,  G06F1/10 ,  G06F9/38 ,  H03K19/0175 ,  G06F13/00

CPC classification number: G06F1/10 ,  G06F9/3869 ,  G06F9/3875

Abstract: A pipelined circuit contains a cascade of stages, each with an intial register followed by a combinatorial logic circuit. The registers are clocked. At the beginning of each clock period, data in the initial register is updated. After that, during the clock period, data propagates from the initial register, along a path through the combinatorial logic circuits, to the initial register in the next stage where it is stored at the beginning of the next cycle. In the path there are several other registers, in which the data is stored at intermdiate phases of the clock cycle, while the data is kept in the initial register. Thus differences in propagation delay along different branches of the path are eliminated without increasing the number of clock cycles needed to pass data through the pipelined circuit. This reduces the number glitches which consume energy without affecting the function of the circuit.

Abstract translation: 流水线电路包含级联级，每级都有一个初始寄存器，后面是组合逻辑电路。 寄存器是时钟。 在每个时钟周期的开始，初始寄存器中的数据被更新。 之后，在时钟周期期间，数据从初始寄存器沿着通过组合逻辑电路的路径传播到在下一个周期开始时被存储的下一个阶段的初始寄存器。 在该路径中，还有几个其他寄存器，其中数据存储在时钟周期的间隔阶段，而数据保存在初始寄存器中。 因此，在不增加通过流水线电路传递数据所需的时钟周期的数量的情况下，消除了沿着路径的不同分支的传播延迟的差异。 这减少了数量毛刺消耗能量，而不影响电路的功能。