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    Design structure including failing address register and compare logic for multi-pass repair of memory arrays
    1.
    发明授权
    Design structure including failing address register and compare logic for multi-pass repair of memory arrays 失效
    设计结构包括故障地址寄存器和用于存储器阵列多次修复的比较逻辑

    公开(公告)号：US08132131B2

    公开(公告)日：2012-03-06

    申请号：US12128197

    申请日：2008-05-28

    申请人： John E. Barth, Jr. ,  Stephen F. Sliva

    发明人： John E. Barth, Jr. ,  Stephen F. Sliva

    IPC分类号： G06F17/50

    CPC分类号： G11C29/24 ,  G11C29/72 ,  G11C2029/4402

    摘要： Disclosed is design structure including an integrated circuit having a system for moving a failing address into a new FAR by utilizing the functional compare circuitry during BIST of redundant memory elements. Disclosed is an any-for-any scheme that eliminates the tri-state address bus. The design structure allows for easy, discrete scaling with the addition of more FARs, while also allowing larger addresses with no additional control circuit overhead.

    摘要翻译： 公开了包括集成电路的集成电路，该集成电路具有通过在冗余存储器元件的BIST期间利用功能比较电路将故障地址移动到新的FAR中的系统。 公开了一种消除三态地址总线的任何方案。 该设计结构允许通过添加更多FAR来实现简单，离散的缩放，同时还允许更大的地址，而无需额外的控制电路开销。

    DESIGN STRUCTURE INCLUDING FAILING ADDRESS REGISTER AND COMPARE LOGIC FOR MULTI-PASS REPAIR OF MEMORY ARRAYS
    2.
    发明申请
    DESIGN STRUCTURE INCLUDING FAILING ADDRESS REGISTER AND COMPARE LOGIC FOR MULTI-PASS REPAIR OF MEMORY ARRAYS 失效
    设计结构，包括失败地址寄存器和比较逻辑，用于存储器阵列的多次修复

    公开(公告)号：US20090158224A1

    公开(公告)日：2009-06-18

    申请号：US12128197

    申请日：2008-05-28

    申请人： John E. Barth, JR. ,  Stephen F. Sliva

    发明人： John E. Barth, JR. ,  Stephen F. Sliva

    IPC分类号： G06F17/50

    CPC分类号： G11C29/24 ,  G11C29/72 ,  G11C2029/4402

    摘要： Disclosed is design structure including an integrated circuit having a system for moving a failing address into a new FAR by utilizing the functional compare circuitry during BIST of redundant memory elements. Disclosed is an any-for-any scheme that eliminates the tri-state address bus. The design structure allows for easy, discrete scaling with the addition of more FARs, while also allowing larger addresses with no additional control circuit overhead.

    摘要翻译： 公开了包括集成电路的集成电路，该集成电路具有通过在冗余存储器元件的BIST期间利用功能比较电路将故障地址移动到新的FAR中的系统。 公开了一种消除三态地址总线的任何方案。 该设计结构允许通过添加更多FAR来实现简单，离散的缩放，同时还允许更大的地址，而无需额外的控制电路开销。

    FAILING ADDRESS REGISTER AND COMPARE LOGIC FOR MULTI-PASS REPAIR OF MEMORY ARRAYS
    3.
    发明申请
    FAILING ADDRESS REGISTER AND COMPARE LOGIC FOR MULTI-PASS REPAIR OF MEMORY ARRAYS 审中-公开
    存储器阵列的多通道修复失败地址寄存器和比较逻辑

    公开(公告)号：US20090154270A1

    公开(公告)日：2009-06-18

    申请号：US11958697

    申请日：2007-12-18

    申请人： John E. Barth Jr. ,  Stephen F. Sliva

    发明人： John E. Barth Jr. ,  Stephen F. Sliva

    IPC分类号： G11C29/04

    CPC分类号： G11C29/24 ,  G11C29/76 ,  G11C2029/1208 ,  G11C2029/4402

    摘要： An integrated circuit having an integrated circuit and method for moving a failing address into a next available FAR by utilizing the functional compare circuitry during BIST of redundant memory elements. A method of is disclosed that includes: providing a set of FARs and an associated set of redundant elements, wherein each FAR maps to a corresponding redundant element; testing a set of elements and placing an address of each failing element into a FAR; testing each redundant element and marking a FAR as bad when a redundant element corresponding to the FAR fails; and readdressing the set of elements and placing an address of an element being readdressed in a new FAR when the address of the element being readdressed matches an address in a FAR that has been marked as bad.

    摘要翻译： 一种集成电路，具有集成电路和方法，用于通过在冗余存储器元件的BIST期间利用功能比较电路将故障地址移动到下一个可用的FAR中。 公开了一种方法，其包括：提供一组FAR和相关的一组冗余元件，其中每个FAR映射到相应的冗余元件; 测试一组元素并将每个故障元素的地址放入FAR中; 当对应于FAR的冗余元素失败时，测试每个冗余元素并将FAR标记为不良; 并且当正被读取的元素的地址与已被标记为不良的FAR中的地址相匹配时，对元素集合进行重新排序并将被读取的元素的地址放置在新的FAR中。