公开(公告)号：US07219314B1

公开(公告)日：2007-05-15

申请号：US10815483

申请日：2004-04-01

申请人： Steven M. Trimberger ,  Shekhar Bapat ,  Robert W. Wells ,  Robert D. Patrie ,  Andrew W. Lai

发明人： Steven M. Trimberger ,  Shekhar Bapat ,  Robert W. Wells ,  Robert D. Patrie ,  Andrew W. Lai

IPC分类号： G06F17/50 ,  G06F11/07 ,  G01R31/3181 ,  G01R31/02

CPC分类号： G01R31/318516

摘要： Described are methods for implementing customer designs in programmable logic devices (PLDs). The defect tolerance of these methods makes them particularly useful with the adoption of “nanotechnology” and molecular-scale technology, or “molectronics.” Test methods identify alternative physical interconnect resources for each net required in the user design and, as need, reroute certain signal paths using the alternative resources. The test methods additionally limit testing to required resources so devices are not rejected as a result of testing performed on unused resources. The tests limit functional testing of used resources to those functions required in the user designs.

摘要翻译： 描述了在可编程逻辑器件（PLD）中实现客户设计的方法。 这些方法的缺陷容忍使得它们对采用“纳米技术”和分子规模技术或“molectronics”尤其有用。 测试方法识别用户设计中所需的每个网络的替代物理互连资源，并根据需要使用替代资源重新路由某些信号路径。 测试方法另外将测试限制为所需的资源，因为在未使用的资源上执行测试的结果，设备不会被拒绝。 测试将功能测试限制在用户设计中所需的功能。