公开(公告)号：US08868634B2

公开(公告)日：2014-10-21

申请号：US13309721

申请日：2011-12-02

申请人： Srikanth Arekapudi ,  Sudherssen Kalaiselvan

发明人： Srikanth Arekapudi ,  Sudherssen Kalaiselvan

IPC分类号： G06F7/533

CPC分类号： G06F7/5338

摘要： A method and apparatus are described for performing multiplication in a processor to generate a product. In one embodiment, a 64-bit multiplier and a 64-bit multiplicand may be multiplied together over four cycles by merging different partial product (PP) subsets, generated by a Booth encoder and a PP generator, with feedback sum and carry results. The logic inputs of a plurality of multiplexers may be selected on a cyclical basis to efficiently compress (i.e., merge) each PP subset with feedback sum and carry results. A pair of preliminary sum results stored during one cycle may be outputted during a subsequent cycle and processed by a logic gate (e.g., an XOR gate) to generate a feedback sum result that is merged with a feedback carry result and a PP subset. Final sum and carry results may be added to generate the product of the multiplier and the multiplicand.

摘要翻译： 描述了用于在处理器中执行乘法以生成乘积的方法和装置。 在一个实施例中，64位乘法器和64位乘法器可以通过将由布斯编码器和PP发生器产生的不同部分乘积（PP）子集合到反馈和和携带结果上而在四个周期内相乘。 可以在循环的基础上选择多个多路复用器的逻辑输入，以有效地压缩（即，合并）具有反馈和的每个PP子集并携带结果。 在一个周期期间存储的一对初步和结果可以在随后的周期期间输出，并由逻辑门（例如，异或门）处理，以产生与反馈进位结果和PP子集合并的反馈和结果。 可以添加最终和携带结果以生成乘数和被乘数的乘积。

公开(公告)号：US20130144927A1

公开(公告)日：2013-06-06

申请号：US13309721

申请日：2011-12-02

申请人： Srikanth Arekapudi ,  Sudherssen Kalaiselvan

发明人： Srikanth Arekapudi ,  Sudherssen Kalaiselvan

IPC分类号： G06F7/523

CPC分类号： G06F7/5338

摘要： A method and apparatus are described for performing multiplication in a processor to generate a product. In one embodiment, a 64-bit multiplier and a 64-bit multiplicand may be multiplied together over four cycles by merging different partial product (PP) subsets, generated by a Booth encoder and a PP generator, with feedback sum and carry results. The logic inputs of a plurality of multiplexers may be selected on a cyclical basis to efficiently compress (i.e., merge) each PP subset with feedback sum and carry results. A pair of preliminary sum results stored during one cycle may be outputted during a subsequent cycle and processed by a logic gate (e.g., an XOR gate) to generate a feedback sum result that is merged with a feedback carry result and a PP subset. Final sum and carry results may be added to generate the product of the multiplier and the multiplicand.

摘要翻译： 描述了用于在处理器中执行乘法以生成乘积的方法和装置。 在一个实施例中，64位乘法器和64位乘法器可以通过将由布斯编码器和PP发生器产生的不同部分乘积（PP）子集合到反馈和和携带结果上而在四个周期内相乘。 可以在循环的基础上选择多个多路复用器的逻辑输入，以有效地压缩（即，合并）具有反馈和的每个PP子集并携带结果。 在一个周期期间存储的一对初步和结果可以在随后的周期期间输出，并由逻辑门（例如，异或门）处理，以产生与反馈进位结果和PP子集合并的反馈和结果。 可以添加最终和携带结果以生成乘数和被乘数的乘积。