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公开(公告)号:US20050135042A1
公开(公告)日:2005-06-23
申请号:US11013789
申请日:2004-12-17
申请人: Victor Chiu-Kit Fong , Eric Blecker , Tom Kwan , Ning Li , Sumant Ranganthan , Chao Tang , Pieter Vorenkamp
发明人: Victor Chiu-Kit Fong , Eric Blecker , Tom Kwan , Ning Li , Sumant Ranganthan , Chao Tang , Pieter Vorenkamp
IPC分类号: H01G4/228
CPC分类号: H01L23/5223 , H01L23/5225 , H01L27/0207 , H01L27/0805 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要: The present invention provides several scalable integrated circuit high density capacitors and their layout techniques. The capacitors are scaled, for example, by varying the number of metal layers and/or the area of the metal layers used to from the capacitors. The capacitors use different metallization patterns to form the metal layers, and different via patterns to couple adjacent metal layers. In embodiments, optional shields are included as the top-most and/or bottom-most layers of the capacitors, and/or as side shields, to reduce unwanted parasitic capacitance.
摘要翻译: 本发明提供了几种可扩展的集成电路高密度电容器及其布局技术。 电容器例如通过改变金属层的数量和/或从电容器使用的金属层的面积来缩放。 电容器使用不同的金属化图案来形成金属层,以及不同的通孔图案以耦合相邻的金属层。 在实施例中,可选屏蔽包括作为电容器的最顶层和/或最底层,和/或作为侧屏蔽,以减少不必要的寄生电容。
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公开(公告)号:US20080266749A1
公开(公告)日:2008-10-30
申请号:US11878696
申请日:2007-07-26
申请人: Victor Chiu-Kit Fong , Eric Bruce Blecker , Tom W. Kwan , Ning Li , Sumant Ranganthan , Chao Tang , Pieter Vorenkamp
发明人: Victor Chiu-Kit Fong , Eric Bruce Blecker , Tom W. Kwan , Ning Li , Sumant Ranganthan , Chao Tang , Pieter Vorenkamp
IPC分类号: H01G4/228
CPC分类号: H01L23/5223 , H01L23/5225 , H01L27/0207 , H01L27/0805 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要: The present invention provides several scalable integrated circuit high density capacitors and their layout techniques. The capacitors are scaled, for example, by varying the number of metal layers and/or the area of the metal layers used to from the capacitors. The capacitors use different metallization patterns to form the metal layers, and different via patterns to couple adjacent metal layers. In embodiments, optional shields are included as the top-most and/or bottom-most layers of the capacitors, and/or as side shields, to reduce unwanted parasitic capacitance.
摘要翻译: 本发明提供了几种可扩展的集成电路高密度电容器及其布局技术。 电容器例如通过改变金属层的数量和/或从电容器使用的金属层的面积来缩放。 电容器使用不同的金属化图案来形成金属层,以及不同的通孔图案以耦合相邻的金属层。 在实施例中,可选屏蔽包括作为电容器的最顶层和/或最底层,和/或作为侧屏蔽,以减少不必要的寄生电容。
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公开(公告)号:US20090283858A1
公开(公告)日:2009-11-19
申请号:US12511398
申请日:2009-07-29
申请人: Victor Chiu-Kit Fong , Eric Bruce Blecker , Tom W. Kwan , Ning Li , Sumant Ranganthan , Chao Tang , Pieter Vorenkamp
发明人: Victor Chiu-Kit Fong , Eric Bruce Blecker , Tom W. Kwan , Ning Li , Sumant Ranganthan , Chao Tang , Pieter Vorenkamp
IPC分类号: H01L27/06
CPC分类号: H01L23/5223 , H01L23/5225 , H01L27/0207 , H01L27/0805 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要: The present invention provides several scalable integrated circuit high density capacitors and their layout techniques. The capacitors are scaled, for example, by varying the number of metal layers and/or the area of the metal layers used to form the capacitors. The capacitors use different metallization patterns to form the metal layers, and different via patterns to couple adjacent metal layers. In embodiments, optional shields are included as the top-most and/or bottom-most layers of the capacitors, and/or as side shields, to reduce unwanted parasitic capacitance.
摘要翻译: 本发明提供了几种可扩展的集成电路高密度电容器及其布局技术。 电容器例如通过改变金属层的数量和/或用于形成电容器的金属层的面积来缩放。 电容器使用不同的金属化图案来形成金属层,以及不同的通孔图案以耦合相邻的金属层。 在实施例中,可选屏蔽包括作为电容器的最顶层和/或最底层,和/或作为侧屏蔽,以减少不必要的寄生电容。
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