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公开(公告)号:USD508541S1
公开(公告)日:2005-08-16
申请号:US29217588
申请日:2004-11-18
申请人: Hiroshi Tsujino , Takahide Sato
设计人: Hiroshi Tsujino , Takahide Sato
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公开(公告)号:USD507604S1
公开(公告)日:2005-07-19
申请号:US29217579
申请日:2004-11-18
申请人: Hiroshi Tsujino , Takahide Sato
设计人: Hiroshi Tsujino , Takahide Sato
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公开(公告)号:USD507022S1
公开(公告)日:2005-07-05
申请号:US29217602
申请日:2004-11-18
申请人: Hiroshi Tsujino , Takahide Sato
设计人: Hiroshi Tsujino , Takahide Sato
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公开(公告)号:USD503433S1
公开(公告)日:2005-03-29
申请号:US29177951
申请日:2003-03-18
申请人: Hiroshi Tsujino , Takahide Sato
设计人: Hiroshi Tsujino , Takahide Sato
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公开(公告)号:US06661289B2
公开(公告)日:2003-12-09
申请号:US10176063
申请日:2002-06-21
申请人: Takahide Sato , Nobuo Fujii , Sigetaka Takagi , Kazuyuki Wada
发明人: Takahide Sato , Nobuo Fujii , Sigetaka Takagi , Kazuyuki Wada
IPC分类号: H03F316
摘要: A voltage-to-current conversion circuit composed of MOSFETs of the same polarity and an OTA with Rail-to-Rail with a simple configuration that uses the same have been disclosed. The voltage-to-current conversion circuit comprises a first MOSFET, to which a fixed drain-source voltage is applied all the time, and which generates a first current signal for an input voltage, a second MOSFET, which has the same polarity as that of the first MOSFET, to which the fixed drain-source voltage is applied all the time, and which generates a second current signal complementary to the first current signal for the input voltage, and a difference current operation circuit that performs the operation of subtraction between the first current signal and the second current signal, thereby an output current is generated in accordance with the input voltage.
摘要翻译: 已经公开了由具有相同极性的MOSFET组成的电压 - 电流转换电路和具有使用它们的简单配置的轨至轨的OTA。 电压 - 电流转换电路包括第一MOSFET,一直施加固定的漏极 - 源极电压,并且其产生用于输入电压的第一电流信号,第二MOSFET具有与之相同极性的第二MOSFET 所述第一MOSFET的固定漏极 - 源极电压一直被施加到所述第一MOSFET,并且产生与所述输入电压的所述第一电流信号互补的第二电流信号;以及差动电流运算电路, 第一电流信号和第二电流信号,从而根据输入电压产生输出电流。
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公开(公告)号:US20090102545A1
公开(公告)日:2009-04-23
申请号:US11917692
申请日:2006-04-25
申请人: Shigetaka Takagi , Nobuo Fujii , Takahide Sato , Kazuyuki Wada
发明人: Shigetaka Takagi , Nobuo Fujii , Takahide Sato , Kazuyuki Wada
IPC分类号: H04B1/10
CPC分类号: H04L25/085
摘要: An input signal (Vin) is divided into n (≧3) number of divided signals which are weighted by first weights (ki). The weighted divided signals are processed by n number of signal processing means 1 to n performing the same signal processing. The processed divided signals are weighted by second weights (li) and added to obtain an output signal (Vout). By selecting the first weights (ki) and the second weights (li), it is possible to eliminate noise or eliminate distortion.
摘要翻译: 输入信号(Vin)被划分成由第一权重(ki)加权的n(> = 3)个分割信号。 加权分频信号由n个信号处理装置1至n执行相同的信号处理。 经处理的分频信号由第二权重(li)加权并相加以获得输出信号(Vout)。 通过选择第一权重(ki)和第二权重(li),可以消除噪声或消除失真。
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公开(公告)号:USD569442S1
公开(公告)日:2008-05-20
申请号:US29287634
申请日:2007-08-30
申请人: Takahide Sato , Naoki Arikawa
设计人: Takahide Sato , Naoki Arikawa
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