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1.发明授权公开(公告)号：US08462285B2
公开(公告)日：2013-06-11
申请号：US12342215
申请日：2008-12-23
申请人： Isao Nojiri , Hiroyuki Murai , Takashi Miyayama
发明人： Isao Nojiri , Hiroyuki Murai , Takashi Miyayama
IPC分类号： G02F1/136
CPC分类号： G02F1/13454
摘要： A first contact hole formed in a gate driving circuit is covered with an electrically conductive oxide film formed to be connected to the first contact hole and having a first pattern. The periphery of the electrically conductive oxide film is surrounded by an electrically conductive oxide film (a sacrifice electrode) formed simultaneously with the electrically conductive oxide film and having a second pattern form.
摘要翻译： 形成在栅极驱动电路中的第一接触孔被形成为连接到第一接触孔并具有第一图案的导电氧化物膜覆盖。 导电氧化物膜的周围由与导电氧化物膜同时形成并具有第二图案形式的导电氧化物膜（牺牲电极）包围。
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公开(公告)号：US08023610B2
公开(公告)日：2011-09-20
申请号：US11968470
申请日：2008-01-02
IPC分类号： G11C19/00
CPC分类号： G11C19/28
摘要： A dual-gate transistor formed of two transistors connected in series between a first power terminal and a first node is used as a charging circuit for charging a gate node (first node) of a transistor intended to pull up an output terminal of a unit shift register. The dual-gate transistor is configured such that the connection node (second node) between the two transistors constituting the dual-gate transistor is pulled down to the L level by the capacitive coupling between the gate and second node in accordance with the change of the gate from the H level to the L level.
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公开(公告)号：US20110122988A1
公开(公告)日：2011-05-26
申请号：US12929472
申请日：2011-01-27
IPC分类号： G11C19/00
CPC分类号： G11C19/28
摘要： A dual-gate transistor formed of two transistors connected in series between a first power terminal and a first node is used as a charging circuit for charging a gate node (first node) of a transistor intended to pull up an output terminal of a unit shift register. The dual-gate transistor is configured such that the connection node (second node) between the two transistors constituting the dual-gate transistor is pulled down to the L level by the capacitive coupling between the gate and second node in accordance with the change of the gate from the H level to the L level.
摘要翻译： 由串联在第一电源端子和第一节点之间的两个晶体管形成的双栅极晶体管用作充电电路，用于对旨在上拉单元偏移的输出端子的晶体管的栅极节点（第一节点）充电 寄存器。 双栅极晶体管被配置为使得构成双栅极晶体管的两个晶体管之间的连接节点（第二节点）根据栅极和第二节点的变化被下拉到L电平 门从H级到L级。
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4.发明申请公开(公告)号：US20090174695A1
公开(公告)日：2009-07-09
申请号：US12342215
申请日：2008-12-23
申请人： Isao Nojiri , Hiroyuki Murai , Takashi Miyayama
发明人： Isao Nojiri , Hiroyuki Murai , Takashi Miyayama
IPC分类号： G09G5/00
CPC分类号： G02F1/13454
摘要： A first contact hole formed in a gate driving circuit is covered with an electrically conductive oxide film formed to be connected to the first contact hole and having a first pattern. The periphery of the electrically conductive oxide film is surrounded by an electrically conductive oxide film (a sacrifice electrode) formed simultaneously with the electrically conductive oxide film and having a second pattern form.
摘要翻译： 形成在栅极驱动电路中的第一接触孔被形成为连接到第一接触孔并具有第一图案的导电氧化物膜覆盖。 导电氧化物膜的周围由与导电氧化物膜同时形成并具有第二图案形式的导电氧化物膜（牺牲电极）包围。
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公开(公告)号：US09244575B2
公开(公告)日：2016-01-26
申请号：US13633420
申请日：2012-10-02
申请人： Masafumi Agari , Naoki Nakagawa , Takeshi Ono , Seiichiro Mori , Takashi Miyayama , Takuji Imamura , Tatsuya Nakamura
发明人： Masafumi Agari , Naoki Nakagawa , Takeshi Ono , Seiichiro Mori , Takashi Miyayama , Takuji Imamura , Tatsuya Nakamura
CPC分类号： G06F3/044
摘要： A touch screen includes a base substrate, a bundle of rectangular wirings in a column direction including a plurality of detection column wirings that are electrically connected in common, and a bundle of rectangular wirings in a row direction including a plurality of detection row wirings that are electrically connected in common, the bundle of wirings being formed on the base substrate. Also, a plurality of block areas obtained by dividing an intersection area in which the bundle of wirings in the column direction and the bundle of wirings in the row direction intersect in a plan view are defined, and only the detection column wiring or only the detection row wiring is provided in each of the block areas.
摘要翻译： 触摸屏包括基底，在列方向上包括多个共同电连接的检测列布线的一束矩形布线，以及包括多个检测列布线的行方向的一束矩形布线， 电连接在一起，所述布线束形成在基底基板上。 此外，通过划分其中列方向上的布线束和行方向上的布线束在平面图中相交的交叉区域而获得的多个块区域，并且仅检测列布线或仅检测 在每个块区域中设置行布线。
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公开(公告)号：US09170689B2
公开(公告)日：2015-10-27
申请号：US13617203
申请日：2012-09-14
CPC分类号： G06F3/044 , G06F3/041 , G06F2203/04103
摘要： A touch screen of a touch panel includes plural detection column wirings and plural detection row wirings that cross the detection column wirings. Dummy column wirings having a similar configuration to that of the detection column wirings are arrayed at further outer sides of outermost detection column wirings out of the plural detection column wirings. Dummy row wirings having a similar configuration to that of the detection row wirings are arrayed at further outer sides of outermost detection row wirings out of the plural detection row wirings.
摘要翻译： 触摸屏的触摸屏包括跨越检测列布线的多个检测列布线和多个检测行布线。 具有与检测列布线类似的配置的虚拟色谱柱布线被排列在多个检测列布线中的最外检测列布线的另外的外侧。 具有与检测行布线类似的配置的虚拟布线布置在多个检测行布线中的最外检测行布线的另外的外侧。
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公开(公告)号：US20090026509A1
公开(公告)日：2009-01-29
申请号：US12115109
申请日：2008-05-05
申请人： Masami Hayashi , Takashi Miyayama , Hiroyuki Murai
发明人： Masami Hayashi , Takashi Miyayama , Hiroyuki Murai
IPC分类号： H01L31/113 , G01T1/24
CPC分类号： H01L31/022408 , H01L27/12 , H01L27/14603 , H01L27/14612 , H01L27/14658
摘要： For a photosensor, an array substrate is provided, wherein the edge of a photodiode is enclosed by the opening edge of a contact hole formed on a drain electrode.
摘要翻译： 对于光传感器，提供阵列基板，其中光电二极管的边缘由形成在漏电极上的接触孔的开口边缘包围。
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公开(公告)号：US20130082964A1
公开(公告)日：2013-04-04
申请号：US13633420
申请日：2012-10-02
申请人： Masafumi AGARI , Naoki Nakagawa , Takeshi Ono , Seiichiro Mori , Takashi Miyayama , Takuji Imamura , Tatsuya Nakamura
发明人： Masafumi AGARI , Naoki Nakagawa , Takeshi Ono , Seiichiro Mori , Takashi Miyayama , Takuji Imamura , Tatsuya Nakamura
IPC分类号： G06F3/041
CPC分类号： G06F3/044
摘要： A touch screen includes a base substrate, a bundle of rectangular wirings in a column direction including a plurality of detection column wirings that are electrically connected in common, and a bundle of rectangular wirings in a row direction including a plurality of detection row wirings that are electrically connected in common, the bundle of wirings being formed on the base substrate. Also, a plurality of block areas obtained by dividing an intersection area in which the bundle of wirings in the column direction and the bundle of wirings in the row direction intersect in a plan view are defined, and only the detection column wiring or only the detection row wiring is provided in each of the block areas.
摘要翻译： 触摸屏包括基底，在列方向上包括多个共同电连接的检测列布线的一束矩形布线，以及包括多个检测列布线的行方向的一束矩形布线， 电连接在一起，所述布线束形成在基底基板上。 此外，通过划分其中列方向上的布线束和行方向上的布线束在平面图中相交的交叉区域而获得的多个块区域，并且仅检测列布线或仅检测 在每个块区域中设置行布线。
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公开(公告)号：US20120207266A1
公开(公告)日：2012-08-16
申请号：US13455808
申请日：2012-04-25
申请人： Youichi TOBITA , Isao Nojiri , Seiichiro Mori , Takashi Miyayama
发明人： Youichi TOBITA , Isao Nojiri , Seiichiro Mori , Takashi Miyayama
IPC分类号： G11C19/00
CPC分类号： G11C19/28 , G09G3/3266 , G09G3/3677 , G09G2300/0408 , G09G2310/0286 , G09G2320/0233 , G11C19/184
摘要： A shift register circuit comprises a first transistor connected between a clock terminal and an output terminal, a second transistor for charging a control electrode of the first transistor in response to activation of an output signal of the preceding stage, a third transistor for discharging the control electrode of the first transistor, an inverter using a control electrode of the third transistor as an output end, and a fourth transistor which discharges an input end of the inverter at power-off and is turned off after power-on. A fifth transistor which is a load element of the inverter charges the control electrode of the third transistor at power-on. It is thereby possible to initialize the respective levels of the nodes without any external initialization signal and prevent a decrease in the level change rate of the output signal in the shift register circuit.
摘要翻译： 移位寄存器电路包括连接在时钟端子和输出端子之间的第一晶体管，用于响应于前一级的输出信号的激活而对第一晶体管的控制电极进行充电的第二晶体管，用于对控制器进行放电的第三晶体管 第一晶体管的电极，使用第三晶体管的控制电极作为输出端的反相器，以及在断电时对逆变器的输入端进行放电并在通电之后被截止的第四晶体管。 作为逆变器的负载元件的第五晶体管在通电时对第三晶体管的控制电极进行充电。 从而可以初始化节点的各个级别而没有任何外部初始化信号，并且防止移位寄存器电路中的输出信号的电平变化率的降低。
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公开(公告)号：US08194817B2
公开(公告)日：2012-06-05
申请号：US12951705
申请日：2010-11-22
申请人： Youichi Tobita , Isao Nojiri , Seiichiro Mori , Takashi Miyayama
发明人： Youichi Tobita , Isao Nojiri , Seiichiro Mori , Takashi Miyayama
IPC分类号： G11C19/00
CPC分类号： G11C19/28 , G09G3/3266 , G09G3/3677 , G09G2300/0408 , G09G2310/0286 , G09G2320/0233 , G11C19/184
摘要： A shift register circuit comprises a first transistor connected between a clock terminal and an output terminal, a second transistor for charging a control electrode of the first transistor in response to activation of an output signal of the preceding stage, a third transistor for discharging the control electrode of the first transistor, an inverter using a control electrode of the third transistor as an output end, and a fourth transistor which discharges an input end of the inverter at power-off and is turned off after power-on. A fifth transistor which is a load element of the inverter charges the control electrode of the third transistor at power-on. It is thereby possible to initialize the respective levels of the nodes without any external initialization signal and prevent a decrease in the level change rate of the output signal in the shift register circuit.
摘要翻译： 移位寄存器电路包括连接在时钟端子和输出端子之间的第一晶体管，用于响应于前一级的输出信号的激活而对第一晶体管的控制电极进行充电的第二晶体管，用于对控制器进行放电的第三晶体管 第一晶体管的电极，使用第三晶体管的控制电极作为输出端的反相器，以及在断电时对逆变器的输入端进行放电并在通电之后被截止的第四晶体管。 作为逆变器的负载元件的第五晶体管在通电时对第三晶体管的控制电极进行充电。 从而可以初始化节点的各个级别而没有任何外部初始化信号，并且防止移位寄存器电路中的输出信号的电平变化率的降低。
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