公开(公告)号：US20130108006A1

公开(公告)日：2013-05-02

申请号：US13718438

申请日：2012-12-18

申请人： Youichi TOBITA

发明人： Youichi TOBITA

IPC分类号： G11C19/28

CPC分类号： G11C19/287 ,  G09G2310/0286 ,  G09G2320/0252 ,  G11C19/28

摘要： An object is to enhance the driving capability and improve the operating speed of a unit shift register applicable to a scanning line driving circuit having a partial display function. A unit shift register forming a gate line driving circuit includes a first transistor that supplies a first clock signal to a first output terminal, a second transistor that supplies a second clock signal to a second output terminal, a third transistor that charges the gate of the first transistor in response to activation of a shift signal of the previous stage, and a fourth transistor connected between the gate of the first transistor and the gate of the second transistor. The first clock signal and the second clock signal have the same phase, and only the second clock signal is activated in a particular period (a display ineffective period).

摘要翻译： 目的是提高驱动能力，提高适用于具有部分显示功能的扫描线驱动电路的单元移位寄存器的操作速度。 形成栅极线驱动电路的单元移位寄存器包括向第一输出端提供第一时钟信号的第一晶体管，向第二输出端提供第二时钟信号的第二晶体管，向第二输出端提供第二时钟信号的第三晶体管， 第一晶体管响应于前一级的移位信号的激活，以及连接在第一晶体管的栅极和第二晶体管的栅极之间的第四晶体管。 第一时钟信号和第二时钟信号具有相同的相位，并且在特定时段（显示无效期）中仅激活第二时钟信号。

公开(公告)号：US20120207266A1

公开(公告)日：2012-08-16

申请号：US13455808

申请日：2012-04-25

申请人： Youichi TOBITA ,  Isao Nojiri ,  Seiichiro Mori ,  Takashi Miyayama

发明人： Youichi TOBITA ,  Isao Nojiri ,  Seiichiro Mori ,  Takashi Miyayama

IPC分类号： G11C19/00

CPC分类号： G11C19/28 ,  G09G3/3266 ,  G09G3/3677 ,  G09G2300/0408 ,  G09G2310/0286 ,  G09G2320/0233 ,  G11C19/184

摘要： A shift register circuit comprises a first transistor connected between a clock terminal and an output terminal, a second transistor for charging a control electrode of the first transistor in response to activation of an output signal of the preceding stage, a third transistor for discharging the control electrode of the first transistor, an inverter using a control electrode of the third transistor as an output end, and a fourth transistor which discharges an input end of the inverter at power-off and is turned off after power-on. A fifth transistor which is a load element of the inverter charges the control electrode of the third transistor at power-on. It is thereby possible to initialize the respective levels of the nodes without any external initialization signal and prevent a decrease in the level change rate of the output signal in the shift register circuit.

摘要翻译： 移位寄存器电路包括连接在时钟端子和输出端子之间的第一晶体管，用于响应于前一级的输出信号的激活而对第一晶体管的控制电极进行充电的第二晶体管，用于对控制器进行放电的第三晶体管 第一晶体管的电极，使用第三晶体管的控制电极作为输出端的反相器，以及在断电时对逆变器的输入端进行放电并在通电之后被截止的第四晶体管。 作为逆变器的负载元件的第五晶体管在通电时对第三晶体管的控制电极进行充电。 从而可以初始化节点的各个级别而没有任何外部初始化信号，并且防止移位寄存器电路中的输出信号的电平变化率的降低。

公开(公告)号：US20120183117A1

公开(公告)日：2012-07-19

申请号：US13428995

申请日：2012-03-23

申请人： Youichi TOBITA

发明人： Youichi TOBITA

IPC分类号： G11C19/00

CPC分类号： G11C19/184 ,  G09G2310/0286 ,  G09G2330/021

摘要： A shift register circuit is provided that can decrease a power consumption caused by a clock signal and can achieve a high driving capacity. A unit shift register has a first transistor that activates an output signal when a power supply potential is provided to an output terminal. A pull-up driving circuit for driving the first transistor has a second transistor for providing a clock signal to a node connected to the gate of the first transistor and a boosting circuit for the node. When an output signal of a preceding stage is activated, the second transistor turns on. Thereafter, when the clock signal is activated, and the node is charged, the second transistor turns off. The boosting circuit increases the potential at the node when the second transistor turns off. Therefore, the first transistor can operate in non-saturation region and activate the output signal.

摘要翻译： 提供一种移位寄存器电路，其可以降低由时钟信号引起的功耗并且可以实现高的驱动能力。 单元移位寄存器具有第一晶体管，当向输出端子提供电源电位时，其激活输出信号。 用于驱动第一晶体管的上拉驱动电路具有第二晶体管，用于向连接到第一晶体管的栅极的节点和节点的升压电路提供时钟信号。 当前一级的输出信号被激活时，第二晶体管导通。 此后，当时钟信号被激活并且节点被充电时，第二晶体管关断。 当第二晶体管截止时，升压电路增加了节点处的电位。 因此，第一晶体管可以在非饱和区域中工作并激活输出信号。

公开(公告)号：US08194817B2

公开(公告)日：2012-06-05

申请号：US12951705

申请日：2010-11-22

申请人： Youichi Tobita ,  Isao Nojiri ,  Seiichiro Mori ,  Takashi Miyayama

发明人： Youichi Tobita ,  Isao Nojiri ,  Seiichiro Mori ,  Takashi Miyayama

IPC分类号： G11C19/00

CPC分类号： G11C19/28 ,  G09G3/3266 ,  G09G3/3677 ,  G09G2300/0408 ,  G09G2310/0286 ,  G09G2320/0233 ,  G11C19/184

摘要： A shift register circuit comprises a first transistor connected between a clock terminal and an output terminal, a second transistor for charging a control electrode of the first transistor in response to activation of an output signal of the preceding stage, a third transistor for discharging the control electrode of the first transistor, an inverter using a control electrode of the third transistor as an output end, and a fourth transistor which discharges an input end of the inverter at power-off and is turned off after power-on. A fifth transistor which is a load element of the inverter charges the control electrode of the third transistor at power-on. It is thereby possible to initialize the respective levels of the nodes without any external initialization signal and prevent a decrease in the level change rate of the output signal in the shift register circuit.

摘要翻译： 移位寄存器电路包括连接在时钟端子和输出端子之间的第一晶体管，用于响应于前一级的输出信号的激活而对第一晶体管的控制电极进行充电的第二晶体管，用于对控制器进行放电的第三晶体管 第一晶体管的电极，使用第三晶体管的控制电极作为输出端的反相器，以及在断电时对逆变器的输入端进行放电并在通电之后被截止的第四晶体管。 作为逆变器的负载元件的第五晶体管在通电时对第三晶体管的控制电极进行充电。 从而可以初始化节点的各个级别而没有任何外部初始化信号，并且防止移位寄存器电路中的输出信号的电平变化率的降低。

公开(公告)号：US08175216B2

公开(公告)日：2012-05-08

申请号：US12647108

申请日：2009-12-24

申请人： Youichi Tobita

发明人： Youichi Tobita

IPC分类号： G11C19/00

CPC分类号： G11C19/184 ,  G09G2310/0286 ,  G09G2330/021

摘要： A shift register circuit is provided that can decrease a power consumption caused by a clock signal and can achieve a high driving capacity. A unit shift register has a first transistor that activates an output signal when a power supply potential is provided to an output terminal. A pull-up driving circuit for driving the first transistor has a second transistor for providing a clock signal to a node connected to the gate of the first transistor and a boosting circuit for the node. When an output signal of a preceding stage is activated, the second transistor turns on. Thereafter, when the clock signal is activated, and the node is charged, the second transistor turns off. The boosting circuit increases the potential at the node when the second transistor turns off. Therefore, the first transistor can operate in non-saturation region and activate the output signal.

摘要翻译： 提供一种移位寄存器电路，其可以降低由时钟信号引起的功耗并且可以实现高的驱动能力。 单元移位寄存器具有第一晶体管，当向输出端子提供电源电位时，其激活输出信号。 用于驱动第一晶体管的上拉驱动电路具有第二晶体管，用于向连接到第一晶体管的栅极的节点和节点的升压电路提供时钟信号。 当前一级的输出信号被激活时，第二晶体管导通。 此后，当时钟信号被激活并且节点被充电时，第二晶体管关断。 当第二晶体管截止时，升压电路增加了节点处的电位。 因此，第一晶体管可以在非饱和区域中工作并激活输出信号。

公开(公告)号：US20120027160A1

公开(公告)日：2012-02-02

申请号：US13270998

申请日：2011-10-11

申请人： Youichi TOBITA

发明人： Youichi TOBITA

IPC分类号： G11C19/00

CPC分类号： G11C19/28 ,  G11C19/184

摘要： A shift register circuit is provided that can suppress a decrease in a drive capability when a frequency of a clock signal increases. A unit shift register includes a first transistor for supplying a clock signal to an output terminal, a pull-up driving circuit for driving the first transistor, a second transistor for discharging the output terminal, and a pull-down driving circuit for driving the second transistor. In the pull-up driving circuit, the gate of a third transistor charging the gate of the first transistor is charged in accordance with activation of an output signal of preceding stage, and the potential at the gate of the third transistor is increased with a capacitive element. As a result, the third transistor operates in the non-saturated region.

摘要翻译： 提供一种移位寄存器电路，其可以抑制当时钟信号的频率增加时的驱动能力的降低。 单元移位寄存器包括用于向输出端子提供时钟信号的第一晶体管，用于驱动第一晶体管的上拉驱动电路，用于对输出端子进行放电的第二晶体管，以及用于驱动第二晶体管的下拉驱动电路 晶体管。 在上拉驱动电路中，对第一晶体管的栅极充电的第三晶体管的栅极根据前级的输出信号的激活而被充电，并且第三晶体管的栅极处的电位随着电容 元件。 结果，第三晶体管在非饱和区域中工作。

公开(公告)号：US08040999B2

公开(公告)日：2011-10-18

申请号：US12606551

申请日：2009-10-27

申请人： Youichi Tobita

发明人： Youichi Tobita

IPC分类号： G11C19/00

CPC分类号： G11C19/28 ,  G11C19/184

摘要： A shift register circuit is provided that can suppress a decrease in a drive capability when a frequency of a clock signal increases. A unit shift register includes a first transistor for supplying a clock signal to an output terminal, a pull-up driving circuit for driving the first transistor, a second transistor for discharging the output terminal, and a pull-down driving circuit for driving the second transistor. In the pull-up driving circuit, the gate of a third transistor charging the gate of the first transistor is charged in accordance with activation of an output signal of preceding stage, and the potential at the gate of the third transistor is increased with a capacitive element. As a result, the third transistor operates in the non-saturated region.

摘要翻译： 提供一种移位寄存器电路，其可以抑制当时钟信号的频率增加时的驱动能力的降低。 单元移位寄存器包括用于向输出端子提供时钟信号的第一晶体管，用于驱动第一晶体管的上拉驱动电路，用于对输出端子进行放电的第二晶体管，以及用于驱动第二晶体管的下拉驱动电路 晶体管。 在上拉驱动电路中，对第一晶体管的栅极充电的第三晶体管的栅极根据前级的输出信号的激活而被充电，并且第三晶体管的栅极处的电位以电容 元件。 结果，第三晶体管在非饱和区域中工作。

公开(公告)号：US20100111245A1

公开(公告)日：2010-05-06

申请号：US12606551

申请日：2009-10-27

申请人： Youichi TOBITA

发明人： Youichi TOBITA

IPC分类号： G11C19/00

CPC分类号： G11C19/28 ,  G11C19/184

摘要： A shift register circuit is provided that can suppress a decrease in a drive capability when a frequency of a clock signal increases. A unit shift register includes a first transistor for supplying a clock signal to an output terminal, a pull-up driving circuit for driving the first transistor, a second transistor for discharging the output terminal, and a pull-down driving circuit for driving the second transistor. In the pull-up driving circuit, the gate of a third transistor charging the gate of the first transistor is charged in accordance with activation of an output signal of preceding stage, and the potential at the gate of the third transistor is increased with a capacitive element. As a result, the third transistor operates in the non-saturated region.

摘要翻译： 提供一种移位寄存器电路，其可以抑制当时钟信号的频率增加时的驱动能力的降低。 单元移位寄存器包括用于向输出端子提供时钟信号的第一晶体管，用于驱动第一晶体管的上拉驱动电路，用于对输出端子进行放电的第二晶体管，以及用于驱动第二晶体管的下拉驱动电路 晶体管。 在上拉驱动电路中，对第一晶体管的栅极充电的第三晶体管的栅极根据前级的输出信号的激活而被充电，并且第三晶体管的栅极处的电位随着电容 元件。 结果，第三晶体管在非饱和区域中工作。

公开(公告)号：US07499518B2

公开(公告)日：2009-03-03

申请号：US11532750

申请日：2006-09-18

申请人： Youichi Tobita ,  Hiroyuki Murai

发明人： Youichi Tobita ,  Hiroyuki Murai

IPC分类号： G11C19/00

CPC分类号： G11C19/184 ,  G09G3/3648 ,  G09G3/3677 ,  G09G2300/0408 ,  G09G2310/027 ,  G11C19/28

摘要： A shift register includes, in the output stage, a first transistor connected between an output terminal and a first clock terminal and a second transistor connected between the output terminal and a first power terminal. Third and fourth transistors constitute an inverter which inverses the level of the gate of the second transistor and outputs it to the gate of the first transistor. An isolation circuit formed by fifth and sixth transistors is provided between the gate of the first transistor and the gate of the fourth transistor. The fifth transistor is diode-connected. When the gate of the first transistor becomes higher than the gate of the fourth transistor, the first and fourth transistors are electrically isolated from each other.

摘要翻译： 移位寄存器包括在输出级中连接在输出端和第一时钟端之间的第一晶体管和连接在输出端和第一电源端之间的第二晶体管。 第三和第四晶体管构成反相器，其反转第二晶体管的栅极的电平并将其输出到第一晶体管的栅极。 由第五晶体管和第六晶体管形成的隔离电路设置在第一晶体管的栅极和第四晶体管的栅极之间。 第五个晶体管是二极管连接的。 当第一晶体管的栅极变得高于第四晶体管的栅极时，第一和第四晶体管彼此电隔离。

公开(公告)号：US07492853B2

公开(公告)日：2009-02-17

申请号：US11625117

申请日：2007-01-19

申请人： Youichi Tobita

发明人： Youichi Tobita

IPC分类号： G11C19/00

CPC分类号： G11C19/28

摘要： A unit shift register includes first and second transistors for supplying low supply voltage to an output terminal. First and second control signals which are complementary to each other are input to first and second control terminals, respectively. A third transistor is connected between the first transistor and first control terminal, and a fourth transistor is connected between the second transistor and second control terminal. The third and fourth transistors each have its drain connected to the gate of each other in a crossed manner.

摘要翻译： 单元移位寄存器包括用于向输出端子提供低电源电压的第一和第二晶体管。 彼此互补的第一和第二控制信号分别输入到第一和第二控制端子。 第三晶体管连接在第一晶体管和第一控制端之间，第四晶体管连接在第二晶体管与第二控制端之间。 第三和第四晶体管各自以交叉的方式将其漏极连接到彼此的栅极。