公开(公告)号：US20120218812A1

公开(公告)日：2012-08-30

申请号：US13349447

申请日：2012-01-12

申请人： Takumi TAKAGI ,  Daisuke Sasaki ,  Masahiko Nishiyama ,  Masatoshi Hasegawa

发明人： Takumi TAKAGI ,  Daisuke Sasaki ,  Masahiko Nishiyama ,  Masatoshi Hasegawa

IPC分类号： G11C5/14

CPC分类号： G11C11/417

摘要： A semiconductor device having an SRAM macro which has a power-off function and facilitates a design associated with a change in storage capacity is provided. The semiconductor device has plural layout units each including a memory array having plural memory cells in an SRAM, a first peripheral circuit that writes data into the memory array and reads the data from the memory array, and a switch group that disconnects the memory array and the first peripheral circuit, and power wires.

摘要翻译： 提供了具有断开功能并有助于与存储容量变化相关联的设计的具有SRAM宏的半导体器件。 半导体器件具有多个布局单元，每个布局单元包括在SRAM中具有多个存储单元的存储器阵列，将数据写入存储器阵列并从存储器阵列读取数据的第一外围电路以及断开存储器阵列和 第一个外围电路和电源线。

公开(公告)号：US08638593B2

公开(公告)日：2014-01-28

申请号：US13349447

申请日：2012-01-12

申请人： Takumi Takagi ,  Daisuke Sasaki ,  Masahiko Nishiyama ,  Masatoshi Hasegawa

发明人： Takumi Takagi ,  Daisuke Sasaki ,  Masahiko Nishiyama ,  Masatoshi Hasegawa

IPC分类号： G11C11/00

CPC分类号： G11C11/417

摘要： A semiconductor device having an SRAM macro which has a power-off function and facilitates a design associated with a change in storage capacity is provided. The semiconductor device has plural layout units each including a memory array having plural memory cells in an SRAM, a first peripheral circuit that writes data into the memory array and reads the data from the memory array, and a switch group that disconnects the memory array and the first peripheral circuit, and power wires.

摘要翻译： 提供了具有断开功能并有助于与存储容量变化相关联的设计的具有SRAM宏的半导体器件。 半导体器件具有多个布局单元，每个布局单元包括在SRAM中具有多个存储单元的存储器阵列，将数据写入存储器阵列并从存储器阵列读取数据的第一外围电路以及断开存储器阵列和 第一个外围电路和电源线。