公开(公告)号：US08181133B2

公开(公告)日：2012-05-15

申请号：US12401982

申请日：2009-03-11

申请人： Tejaswi Gowda ,  Sarma Vrudhula

发明人： Tejaswi Gowda ,  Sarma Vrudhula

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G06F17/504

摘要： Aspects of a method and system for combinational equivalence checking for threshold logic circuits are provided. In this regard, one or more inputs may be received at a threshold logic gate. The threshold function of the threshold logic gate may be recursively decomposed into a first function and a second function using cofactors of the threshold function. A Boolean function representation of the threshold logic gate may be generated based on the recursive decomposition of the threshold function. The generated Boolean function representation of the threshold logic gate may be a maximally factored form representation of a minimal sum of products (SOP) for the threshold logic gate. A logical equivalence of the threshold logic gate may be verified with one or more other logic circuits based on the generated Boolean function representation of the threshold logic gate.

摘要翻译： 提供了一种用于阈值逻辑电路的组合等价性检查的方法和系统。 在这方面，可以在阈值逻辑门处接收一个或多个输入。 阈值逻辑门的阈值函数可以使用阈值函数的辅因子递归地分解为第一函数和第二函数。 可以基于阈值函数的递归分解来生成阈值逻辑门的布尔函数表示。 阈值逻辑门的生成的布尔函数表示可以是用于阈值逻辑门的产品的最小和（SOP）的最大因子形式表示。 可以基于生成的阈值逻辑门的布尔函数表示，用一个或多个其他逻辑电路来验证阈值逻辑门的逻辑等价。

公开(公告)号：US20230113589A1

公开(公告)日：2023-04-13

申请号：US17962460

申请日：2022-10-07

申请人： Karthik Kashinath Kulkarni ,  Suren Jayasuriya ,  Ariane Middel ,  Tejaswi Gowda ,  Florian Arwed Schneider

发明人： Karthik Kashinath Kulkarni ,  Suren Jayasuriya ,  Ariane Middel ,  Tejaswi Gowda ,  Florian Arwed Schneider

IPC分类号： G06V20/10 ,  G06V10/70 ,  G06V40/10 ,  G06V10/94 ,  G01W1/04

摘要： The disclosure concerns biometeorological sensing devices including a processor communicatively coupled to a memory, and a plurality of sensors communicatively coupled to the processor. The plurality of sensors includes a humidity sensor, a UV sensor, an anemometer, an atmospheric thermometer, a globe thermometer, and a camera. The device also includes a network interface communicatively coupled to the processor. The processor is configured to estimate a mean radiant temperature (MRT) using data received from the plurality of sensors, identify a person in an image received from the camera, determine a bounding box that encloses the person in the image, generate a shadow map from the image, calculate an intersection over union (IOU) of the bounding box with the shadow map to determine if the person is in the shade, and transmit observed space usage and estimated MRT to a server communicatively coupled to the network interface.

公开(公告)号：US08601417B2

公开(公告)日：2013-12-03

申请号：US13090796

申请日：2011-04-20

申请人： Tejaswi Gowda ,  Sarma Vrudhula

发明人： Tejaswi Gowda ,  Sarma Vrudhula

IPC分类号： G06F17/50

CPC分类号： G06F17/505

摘要： Systems and methods for identifying a Boolean function as either a threshold function or a non-threshold function are disclosed. In one embodiment, in order to identify a Boolean function as either a threshold function or a non-threshold function, a determination is first made as to whether the Boolean function satisfies one or more predefined conditions for being a threshold function, where the one or more predefined conditions include a condition that both a positive cofactor and a negative cofactor of the Boolean function are threshold functions. If the one or more predefined conditions are satisfied, a determination is made as to whether weights for the positive and negative cofactors are equal. If the weights for the cofactors are equal, then the Boolean function is determined to be a threshold function. Further, in one embodiment, this threshold function identification process is utilized in a threshold circuit synthesis process.

摘要翻译： 公开了用于将布尔函数识别为阈值函数或非阈值函数的系统和方法。 在一个实施例中，为了将布尔函数识别为阈值函数或非阈值函数，首先确定布尔函数是否满足作为阈值函数的一个或多个预定义条件，其中，一个或 更多的预定义条件包括布尔函数的正辅助因子和负辅助因子都是阈值函数的条件。 如果满足一个或多个预定条件，则确定正和负辅助因子的权重是否相等。 如果辅因子的权重相等，则布尔函数被确定为阈值函数。 此外，在一个实施例中，该阈值函数识别处理被用于阈值电路合成处理。

公开(公告)号：US20110214095A1

公开(公告)日：2011-09-01

申请号：US13090796

申请日：2011-04-20

申请人： Tejaswi Gowda ,  Sarma Vrudhula

发明人： Tejaswi Gowda ,  Sarma Vrudhula

IPC分类号： G06F17/50

CPC分类号： G06F17/505

摘要： Systems and methods for identifying a Boolean function as either a threshold function or a non-threshold function are disclosed. In one embodiment, in order to identify a Boolean function as either a threshold function or a non-threshold function, a determination is first made as to whether the Boolean function satisfies one or more predefined conditions for being a threshold function, where the one or more predefined conditions include a condition that both a positive cofactor and a negative cofactor of the Boolean function are threshold functions. If the one or more predefined conditions are satisfied, a determination is made as to whether weights for the positive and negative cofactors are equal. If the weights for the cofactors are equal, then the Boolean function is determined to be a threshold function. Further, in one embodiment, this threshold function identification process is utilized in a threshold circuit synthesis process.

摘要翻译： 公开了用于将布尔函数识别为阈值函数或非阈值函数的系统和方法。 在一个实施例中，为了将布尔函数识别为阈值函数或非阈值函数，首先确定布尔函数是否满足作为阈值函数的一个或多个预定义条件，其中，一个或 更多的预定义条件包括布尔函数的正辅助因子和负辅助因子都是阈值函数的条件。 如果满足一个或多个预定条件，则确定正和负辅助因子的权重是否相等。 如果辅因子的权重相等，则布尔函数被确定为阈值函数。 此外，在一个实施例中，该阈值函数识别处理被用于阈值电路合成处理。

公开(公告)号：US20090235216A1

公开(公告)日：2009-09-17

申请号：US12401982

申请日：2009-03-11

申请人： Tejaswi Gowda ,  Sarma Vrudhula

发明人： Tejaswi Gowda ,  Sarma Vrudhula

IPC分类号： G06F17/50

CPC分类号： G06F17/504

摘要： Aspects of a method and system for combinational equivalence checking for threshold logic circuits are provided. In this regard, one or more inputs may be received at a threshold logic gate. The threshold function of the threshold logic gate may be recursively decomposed into a first function and a second function using cofactors of the threshold function. A Boolean function representation of the threshold logic gate may be generated based on the recursive decomposition of the threshold function. The generated Boolean function representation of the threshold logic gate may be a maximally factored form representation of a minimal sum of products (SOP) for the threshold logic gate. A logical equivalence of the threshold logic gate may be verified with one or more other logic circuits based on the generated Boolean function representation of the threshold logic gate.

摘要翻译： 提供了一种用于阈值逻辑电路的组合等价性检查的方法和系统。 在这方面，可以在阈值逻辑门处接收一个或多个输入。 阈值逻辑门的阈值函数可以使用阈值函数的辅因子递归地分解为第一函数和第二函数。 可以基于阈值函数的递归分解来生成阈值逻辑门的布尔函数表示。 阈值逻辑门的生成的布尔函数表示可以是用于阈值逻辑门的产品的最小和（SOP）的最大因子形式表示。 可以基于生成的阈值逻辑门的布尔函数表示，用一个或多个其他逻辑电路来验证阈值逻辑门的逻辑等价。