公开(公告)号：US4723224A

公开(公告)日：1988-02-02

申请号：US815610

申请日：1986-01-02

申请人： Terry Van Hulett ,  Jesse R. Wilson ,  Ralph McGarity

发明人： Terry Van Hulett ,  Jesse R. Wilson ,  Ralph McGarity

IPC分类号： G06F17/30 ,  G11C15/04 ,  G11C15/00

CPC分类号： G06F17/30982 ,  G11C15/04

摘要： A content addressable memory (CAM) comprising a plurality of CAM cells, each including a static read/write memory (RWM) cell and an EXCLUSIVE OR (XOR) gate which couples a sense line to a ground line only if the logic state of the operand bit stored in the RWM cell does not match the logic state of an operand bit presented to the CAM cell. By arranging a selected subset of the CAM cells so that the XOR gates thereof act upon a first portion of either the sense line or the ground line while the balance of the CAM cells are arranged so that the XOR gates thereof act upon a second portion of that same line, a single coupler interposed between the first and second portions can be selectively disabled by a mask signal to simultaneously mask all of the bits stored in the subset of CAM cells during the matching operation of the CAM. If appropriate, the mask signal may comprise the bit stored in a particular one of the CAM cells.

摘要翻译： 一种内容可寻址存储器（CAM），包括多个CAM单元，每个单元包括静态读/写存储器（RWM）单元和唯一或（异或）门，其仅在所述CAM单元的逻辑状态 存储在RWM单元中的操作数位与呈现给CAM单元的操作数位的逻辑状态不匹配。 通过布置CAM单元的所选择的子集，使得其XOR门作用在感测线或接地线的第一部分上，同时CAM单元的平衡被布置成使其XOR门作用在第二部分 插入在第一和第二部分之间的单个耦合器可以被掩模信号选择性地禁用，以在CAM的匹配操作期间同时掩蔽存储在CAM单元的子集中的所有位。 如果适当，掩码信号可以包括存储在特定的一个CAM单元中的位。