Method for preserving regularity during logic synthesis
    1.
    发明授权
    Method for preserving regularity during logic synthesis 失效
    在逻辑合成期间保持规律性的方法

    公开(公告)号:US06557159B1

    公开(公告)日:2003-04-29

    申请号:US09578090

    申请日:2000-05-24

    IPC分类号: G06F1750

    CPC分类号: G06F17/505

    摘要: The present invention concerns a method for maintaining regularity in a netlist during logic synthesis. The method determines a global regularity for the netlist. The method determines a group of elements in the netlist having similar regularity signatures. Further, the method applies a transform to the group of elements.

    摘要翻译: 本发明涉及一种在逻辑综合期间维持网表规则性的方法。 该方法确定网表的全局规律性。 该方法确定具有相似规则性签名的网表中的一组元素。 此外,该方法将变换应用于该组元素。