公开(公告)号：US5448493A

公开(公告)日：1995-09-05

申请号：US456010

申请日：1989-12-20

申请人： Todd J. Topolewski ,  Christine M. Weir ,  Bart Reynolds ,  Julia M. Smuts ,  Pardner Wynn ,  Stephen M. Trimberger

发明人： Todd J. Topolewski ,  Christine M. Weir ,  Bart Reynolds ,  Julia M. Smuts ,  Pardner Wynn ,  Stephen M. Trimberger

IPC分类号： G06F17/50 ,  G06F15/60

CPC分类号： G06F17/5072 ,  G06F17/5054

摘要： Highly integrated programmable arrays, in which a logic array integrated circuit chip is divided into configurable logic blocks interconnected by configurable interconnect lines, have been programmed by automatic means and methods. The present invention provides for allowing a user to manually specify the partitioning of a logic design, and to allow a user to retain portions of a previously partitioned, placed, and routed design when making revisions. To allow for manual control of partitioning, a library of symbols includes a partitioning symbol that specifies which primitive logic functions can be grouped. The user specifies which ports of primitive logic functions will correspond with ports on the logic block symbol. The present invention also allows for partitioning parts of a design before combining the parts.

摘要翻译： 高度集成的可编程阵列（其中将逻辑阵列集成电路芯片划分为可配置互连线互连的可配置逻辑块）已经通过自动化手段和方法编程。 本发明提供允许用户手动指定逻辑设计的划分，并且允许用户在进行修改时保留先前分割的，放置的和路由的设计的部分。 为了允许对分区进行手动控制，符号库包括一个分配符号，用于指定哪些原始逻辑功能可以分组。 用户指定原始逻辑功能的哪些端口将对应于逻辑块符号上的端口。 本发明还允许在组合部件之前对设计的部分进行分区。