公开(公告)号：US20060150023A1

公开(公告)日：2006-07-06

申请号：US11297387

申请日：2005-12-09

申请人： Tomoya Hasebe ,  Shinya Miyaji ,  Kazuhide Watanabe

发明人： Tomoya Hasebe ,  Shinya Miyaji ,  Kazuhide Watanabe

IPC分类号： G06F11/00

CPC分类号： G01R31/31705 ,  G06F11/2242

摘要： To efficiently debug while reducing a debugging circuit in a system LSI made up of a plurality of CPUs. A debugging apparatus includes debug object selection means 109 for selecting the CPU to be debugged from CPUs 11 and 12 in accordance with a debug object selection request from a host PC 15 connected to a system LSI 17, event information output means 110 for outputting internal event information of one selected CPU to be debugged, detected event storage means 106 for temporarily storing a detected event set by the host PC 15, and event comparison means 105 for making a comparison between the internal event information output from the event information output means 110 and the detected event stored in the detected event storage means 106 to detect a match therebetween. The event comparison means 105 notifies the host PC 15 that an event match is detected.

摘要翻译： 在减少由多个CPU构成的系统LSI中的调试电路的同时有效调试。 调试装置包括调试对象选择装置109，用于根据来自连接到系统LSI 17的主机PC 15的调试对象选择请求从CPU11和12中选择要调试的CPU，调试对象选择装置109，用于输出内部事件的事件信息输出装置110 要被调试的一个所选择的CPU的信息，用于临时存储由主机15设置的检测到的事件的检测事件存储装置106以及用于进行从事件信息输出装置110输出的内部事件信息和 检测到的事件存储在检测事件存储装置106中以检测它们之间的匹配。 事件比较装置105通知主机PC 15检测到事件匹配。