公开(公告)号：US6150235A

公开(公告)日：2000-11-21

申请号：US490275

申请日：2000-01-24

申请人： Yih-Yuh Doong ,  Sung-Chun Hsieh ,  Tsu-Bin Shen ,  Ching-Hsiang Hsu

发明人： Yih-Yuh Doong ,  Sung-Chun Hsieh ,  Tsu-Bin Shen ,  Ching-Hsiang Hsu

IPC分类号： H01L21/762 ,  H01L21/8238 ,  H01L21/76

CPC分类号： H01L21/76237 ,  H01L21/823878

摘要： A method for forming shallow trench isolation (STI) structures on a semiconductor substrate is disclosed. First a semiconductor substrate with a first area and a second area adjacent to the first area is provided. A mask layer is formed on the substrate, and is etched to expose portions of the substrate. A first photoresist is formed to cover the second area for exposing the first area. A first implanting procedure is performed with a titled angle to form first doping areas on the substrate encroaching into portions of the substrate covered by the first photoresist. The first photoresist is removed. A second photoresist is formed on the substrate to cover the first area for exposing the second area. And a second implanting procedure is done with a titled angle to form second doping areas on the substrate encroaching into portions of the substrate covered by the second photoresist. The second photoresist is removed. The substrate is etched to remove the first doping areas and the second doping areas for forming trench structures therein. It is noted that portions of the first doping areas and the second doping areas are residual in upper portions of sidewalls of the trench structures adjacent to the mask layer. Then the shallow trench isolations are formed in the trench structures.

摘要翻译： 公开了一种在半导体衬底上形成浅沟槽隔离（STI）结构的方法。 首先，提供具有与第一区域相邻的第一区域和第二区域的半导体衬底。 掩模层形成在衬底上，并被蚀刻以暴露衬底的部分。 形成第一光致抗蚀剂以覆盖用于暴露第一区域的第二区域。 以标题角度执行第一植入过程，以在衬底上形成侵蚀到由第一光致抗蚀剂覆盖的衬底的部分中的第一掺杂区域。 去除第一光致抗蚀剂。 在基板上形成第二光致抗蚀剂以覆盖用于暴露第二区域的第一区域。 并且以标题角完成第二种植入过程，以在衬底上形成侵蚀到由第二光致抗蚀剂覆盖的衬底的部分中的第二掺杂区域。 去除第二光致抗蚀剂。 蚀刻衬底以除去第一掺杂区域和用于在其中形成沟槽结构的第二掺杂区域。 要注意的是，第一掺杂区域和第二掺杂区域的部分在与掩模层相邻的沟槽结构的侧壁的上部残留。 然后在沟槽结构中形成浅沟槽隔离。

公开(公告)号：US06396751B1

公开(公告)日：2002-05-28

申请号：US09755547

申请日：2001-01-05

申请人： Yih-Yuh Doong ,  Tsu-bin Shen ,  Sung Chun Hsieh ,  Chien-Jung Wang

发明人： Yih-Yuh Doong ,  Tsu-bin Shen ,  Sung Chun Hsieh ,  Chien-Jung Wang

IPC分类号： G11C700

CPC分类号： G11C29/025 ,  G11C11/401 ,  G11C29/02 ,  G11C29/50 ,  G11C2029/5002

摘要： A semiconductor memory device comprising a test structure is disclosed. The semiconductor device includes a plurality of memory cells, word lines, bit lines, and test pads; the word lines including a first set and a second set of word lines, connected to a first and second word line test pad, respectively; the bit lines including a first set and a second set of bit lines, connected to a first and second bit line test pad, respectively. The first set of word lines and the first set of bit lines access a first set of memory cells, the first set of word lines and the second set of bit lines access a second set of memory cells, the second set of word lines and the first set of bit lines access a third set of memory cells, and the second set of word lines and the second set of bit lines access a fourth set of memory cells. By applying a predetermined set of test signals to the first and second word line test pads, and the first and second bit line test pads, the disturbance or interference among the first, second, third, and fourth set of memory cells can be measured.

摘要翻译： 公开了一种包括测试结构的半导体存储器件。 半导体器件包括多个存储器单元，字线，位线和测试焊盘; 所述字线包括分别连接到第一和第二字线测试板的第一组和第二组字线; 位线包括分别连接到第一和第二位线测试焊盘的第一组和第二组位线。 第一组字线和第一组位线访问第一组存储器单元，第一组字线和第二组位线访问第二组存储器单元，第二组字线和 第一组位线访问第三组存储器单元，并且第二组字线和第二组位线访问第四组存储器单元。 通过将预定的一组测试信号施加到第一和第二字线测试焊盘以及第一和第二位线测试焊盘，可以测量第一，第二，第三和第四组存储器单元之间的干扰或干扰。