公开(公告)号：US07103738B2

公开(公告)日：2006-09-05

申请号：US10647260

申请日：2003-08-26

申请人： Takashi Yoneda ,  Tsutomu Kamiyoshi ,  Hiroshi Benno ,  Shirou Yoshioka ,  Tsuneo Uenishi

发明人： Takashi Yoneda ,  Tsutomu Kamiyoshi ,  Hiroshi Benno ,  Shirou Yoshioka ,  Tsuneo Uenishi

IPC分类号： G06F12/16 ,  G06F12/11

CPC分类号： G06F13/28

摘要： A backup memory, a DMA (direct memory access) controller, and a WDT (watch dog timer) are provided in addition to a CPU (central processing unit), a RAM (random access memory), and a peripheral circuit. The DMA controller exercises control so that respective data of the CPU, RAM and peripheral circuit is saved in the backup memory each time the CPU, being under normal operation, supplies a counter reset signal to the WDT, and so that the data that has been saved in the backup memory is restored to the CPU, the RAM and the peripheral circuit, respectively, if the WDT has detected a program runaway and outputted a time-over signal. Therefore, even in a case where a program runaway has occurred in the CPU, normal operation is permitted to be resumed from midway in the program.

摘要翻译： 除了CPU（中央处理单元），RAM（随机存取存储器）和外围电路之外，还提供备用存储器，DMA（直接存储器访问）控制器和WDT（看门狗定时器）。 DMA控制器进行控制，以使CPU，RAM和外围电路的每个数据都保存在备用存储器中，每当处于正常操作状态的CPU向WDT提供计数器复位信号时， 如果WDT检测到程序失控并输出超时信号，则保存在备份存储器中的数据被分别还原到CPU，RAM和外围电路。 因此，即使在CPU中发生程序失控的情况下，也可以在程序的中途恢复正常的动作。