公开(公告)号：US20060117240A1

公开(公告)日：2006-06-01

申请号：US10985475

申请日：2004-11-10

申请人： Vladimir Novichkov ,  Tom Richardson ,  Vince Loncke

发明人： Vladimir Novichkov ,  Tom Richardson ,  Vince Loncke

IPC分类号： H03M13/00

CPC分类号： H03M13/116 ,  H03M13/1137

摘要： High throughput parallel LDPC decoders are designed and implemented using hierarchical design and layout optimization. In a first level of hierarchy, the node processors are grouped on the LDPC decoder chip, physically co-locating the processing elements in a small area. In a second level of hierarchy, clusters, e.g., subsets, of the processing elements are grouped together and a pipeline stage including pipeline registers is introduced on the boundaries between clusters. Register to register path propagating signals are keep localized as much as possible. The switching fabric coupling the node processors with edge message memory is partitioned into separate switches. Each separate switch is split into combinational switching layers. Design hierarchies are created for each layer, localizing the area where the interconnect is dense and resulting in short interconnect paths thus limiting signal delays in routing.

公开(公告)号：US07617432B2

公开(公告)日：2009-11-10

申请号：US10985475

申请日：2004-11-10

申请人： Vladimir Novichkov ,  Tom Richardson ,  Vince Loncke

发明人： Vladimir Novichkov ,  Tom Richardson ,  Vince Loncke

IPC分类号： H03M13/11

CPC分类号： H03M13/116 ,  H03M13/1137

摘要： High throughput parallel LDPC decoders are designed and implemented using hierarchical design and layout optimization. In a first level of hierarchy, the node processors are grouped on the LDPC decoder chip, physically co-locating the processing elements in a small area. In a second level of hierarchy, clusters, e.g., subsets, of the processing elements are grouped together and a pipeline stage including pipeline registers is introduced on the boundaries between clusters. Register to register path propagating signals are keep localized as much as possible. The switching fabric coupling the node processors with edge message memory is partitioned into separate switches. Each separate switch is split into combinational switching layers. Design hierarchies are created for each layer, localizing the area where the interconnect is dense and resulting in short interconnect paths thus limiting signal delays in routing.

摘要翻译： 高吞吐量并行LDPC解码器采用分层设计和布局优化设计和实现。 在第一层次结构中，节点处理器被分组在LDPC解码器芯片上，将处理元件物理上共同定位在小区域中。 在第二级别中，将处理元件的集群（例如子集）分组在一起，并且在集群之间的边界上引入包括流水线寄存器的流水线级。 寄存器寄存器路径传播信号尽可能地保持本地化。 将节点处理器与边缘消息存储器耦合的交换结构被划分为单独的交换机。 每个单独的开关分为组合开关层。 为每个层创建设计层次结构，将互连密集区域进行本地化，并产生短互连路径，从而限制路由中的信号延迟。