Abstract:
A transportable fuel emulsion blending system is provided. The disclosed embodiments of the transportable fuel emulsion blending system includes a plurality of fluid circuits, including a hydrocarbon circuit, a fuel emulsion additive circuit, a water circuit and an optional alcohol/methanol circuit all of which are disposed on a transportable platform such as a vehicle or moveable skid.
Abstract:
A fuel emulsion blending system and method for operating the same is provided. The disclosed embodiments of the fuel emulsion blending system includes a plurality of fluid circuits, including a hydrocarbon circuit, a fuel emulsion additive circuit, a water circuit and an optional alcohol/methanol circuit. Each of the inlet circuits are adapted for receiving the identified ingredient from a suitable source which optionally may be included as part of the blending system. The disclosed blending system further includes a first blending station adapted to mix the hydrocarbon fuel and fuel emulsion additives and a second blending station adapted to mix the hydrocarbon fuel and additive mixture received from the first blending station together with the water received from the source of water. The disclosed blending system further includes an emulsification station downstream of the blending stations which is adapted to emulsify the mixture of hydrocarbon fuel, additives and water to yield a stable fuel emulsion.
Abstract:
A microprocessor architecture including a finite state machine in combination with a microcode instruction cache for executing microinstructions. Microinstructions which would normally result in small sequences of high-repetition looped operations are implemented in a finite state machine (FSM). The use of the FSM is more energy-efficient than looping instructions in a cache or register set. In addition, the flexibility of a cache, or other memory oriented approach, in executing microcode instructions is still available. A microinstruction is identified as an FSM operation (as opposed to a cache operation) by an ID tag. Other fields of the microinstruction can be used to identify the type of FSM circuitry to use, direct configuration of a FSM to implement the microinstruction, indicate that certain fields are to be implemented in one or more FSMs and/or in memory-oriented operations such as in a cache or register.
Abstract:
A video processor according to the invention is dynamically configurable as to the attributes of the video data upon which the processor operates. Some embodiments dynamically configure the processor via a sequence of instructions, where the instructions include information on the attributes of the current video data. Some embodiments include a dynamically configurable adder array that computes difference functions thereby generating error vectors. Some embodiments include a dynamically configurable adder array that computes filtering functions applied to the video data, e.g. interpolation or decimation of the incoming video prior to motion detection. Some embodiments of the invention provide dynamically configurable hardware searches, for example, for detecting motion. Some embodiments of the invention are implemented using an adaptive computing machines (ACMs). An ACM includes a plurality of heterogeneous computational elements, each coupled to an interconnection network.