公开(公告)号：US20110254595A1

公开(公告)日：2011-10-20

申请号：US13087021

申请日：2011-04-14

Applicant: Weigang Sun

Inventor： Weigang Sun

IPC: H03B19/06 ,  H03K3/356 ,  H03K3/00

CPC classification number: H03K3/356139 ,  H03K21/10 ,  H03K23/00

Abstract: Various embodiments of a flip-flop and a frequency dividing circuit are provided. In one aspect, a flip-flop includes an input stage and a latch stage. The input stage is capable of converting an input signal to an output signal under the control of a first clock signal and a second clock signal. The latch stage is capable of latching the output signal under the control of a third clock signal and a fourth clock signal. The first clock signal, the second clock signal, the third clock signal and the fourth clock signal have different phases.

Abstract translation: 提供了触发器和分频电路的各种实施例。 一方面，触发器包括输入级和锁存级。 输入级能够在第一时钟信号和第二时钟信号的控制下将输入信号转换为输出信号。 锁存级能够在第三时钟信号和第四时钟信号的控制下锁存输出信号。 第一时钟信号，第二时钟信号，第三时钟信号和第四时钟信号具有不同的相位。

公开(公告)号：US08760207B2

公开(公告)日：2014-06-24

申请号：US13087021

申请日：2011-04-14

Applicant: Weigang Sun

Inventor： Weigang Sun

IPC: H03K3/356 ,  H03K21/10 ,  H03K23/00

CPC classification number: H03K3/356139 ,  H03K21/10 ,  H03K23/00

Abstract: Various embodiments of a flip-flop and a frequency dividing circuit are provided. In one aspect, a flip-flop includes an input stage and a latch stage. The input stage is capable of converting an input signal to an output signal under the control of a first clock signal and a second clock signal. The latch stage is capable of latching the output signal under the control of a third clock signal and a fourth clock signal. The first clock signal, the second clock signal, the third clock signal and the fourth clock signal have different phases.

Abstract translation: 提供了触发器和分频电路的各种实施例。 一方面，触发器包括输入级和锁存级。 输入级能够在第一时钟信号和第二时钟信号的控制下将输入信号转换为输出信号。 锁存级能够在第三时钟信号和第四时钟信号的控制下锁存输出信号。 第一时钟信号，第二时钟信号，第三时钟信号和第四时钟信号具有不同的相位。

公开(公告)号：US20100233984A1

公开(公告)日：2010-09-16

申请号：US12401162

申请日：2009-03-10

Applicant: Chao-Tung YANG ,  Hung Chuan Pai ,  Weigang Sun

Inventor： Chao-Tung YANG ,  Hung Chuan Pai ,  Weigang Sun

IPC: H04B1/10

CPC classification number: H04B1/1036

Abstract: The invention discloses an interference cancellation circuit for a receiver to process an input signal which is carried on a first carrier frequency and includes a transmitted signal and at least one interference signals. The interference cancellation circuit comprises a down-converter for converting the input signal to dc location to generate a down-converted signal; a first path circuit for processing the down-converted signal to generate a first processed signal which includes the transmitted signal and the interference signals; a second path circuit for processing the down-converted signal to generate a second processed signal which includes only the interference signals; and a combiner for generating an output signal by combining the first processed signal and the second processed signal.

Abstract translation: 本发明公开了一种用于接收机处理在第一载波频率上承载的输入信号并包括发射信号和至少一个干扰信号的干扰消除电路。 干扰消除电路包括用于将输入信号转换为直流位置以产生下变频信号的下变频器; 用于处理下变频信号以产生包括发射信号和干扰信号的第一处理信号的第一路径电路; 用于处理下变频信号以产生仅包括干扰信号的第二处理信号的第二路径电路; 以及组合器，用于通过组合第一处理信号和第二处理信号来产生输出信号。

公开(公告)号：US08396439B2

公开(公告)日：2013-03-12

申请号：US12401162

申请日：2009-03-10

Applicant: Chao-Tung Yang ,  Hung Chuan Pai ,  Weigang Sun

Inventor： Chao-Tung Yang ,  Hung Chuan Pai ,  Weigang Sun

IPC: H04B1/10

CPC classification number: H04B1/1036

Abstract: The invention discloses an interference cancellation circuit for a receiver to process an input signal which is carried on a first carrier frequency and includes a transmitted signal and at least one interference signals. The interference cancellation circuit comprises a down-converter for converting the input signal to dc location to generate a down-converted signal; a first path circuit for processing the down-converted signal to generate a first processed signal which includes the transmitted signal and the interference signals; a second path circuit for processing the down-converted signal to generate a second processed signal which includes only the interference signals; and a combiner for generating an output signal by combining the first processed signal and the second processed signal.

Abstract translation: 本发明公开了一种用于接收机处理在第一载波频率上承载的输入信号并包括发射信号和至少一个干扰信号的干扰消除电路。 干扰消除电路包括用于将输入信号转换为直流位置以产生下变频信号的下变频器; 用于处理下变频信号以产生包括发射信号和干扰信号的第一处理信号的第一路径电路; 用于处理下变频信号以产生仅包括干扰信号的第二处理信号的第二路径电路; 以及组合器，用于通过组合第一处理信号和第二处理信号来产生输出信号。