公开(公告)号：US20080192535A1

公开(公告)日：2008-08-14

申请号：US12068983

申请日：2008-02-14

Applicant: Whee-jin Kwon ,  Jung-hwa Lee

Inventor： Whee-jin Kwon ,  Jung-hwa Lee

IPC: G11C11/34 ,  G11C7/00

CPC classification number: G11C7/065 ,  G11C7/12 ,  H01L27/0207 ,  H01L27/11803 ,  H01L29/66621

Abstract: A sense amplifier includes a first transistor having a gate electrode electrically connected to a bit line and a first electrode electrically connected to a complementary bit line. A second transistor has a gate electrode electrically connected to the complementary bit line and a first electrode electrically connected to the bit line. An equalizing transistor is disposed between the gate electrode of the first transistor and the gate electrode of the second transistor. The first electrode of the first transistor and a first electrode of the equalizing transistor are electrically connected to each other, and the first electrode of the second transistor and a second electrode of the equalizing transistor are electrically connected to each other.

Abstract translation: 读出放大器包括：第一晶体管，其具有电连接到位线的栅电极和与互补位线电连接的第一电极。 第二晶体管具有电连接到互补位线的栅电极和电连接到位线的第一电极。 在第一晶体管的栅电极和第二晶体管的栅电极之间设置均衡晶体管。 第一晶体管的第一电极和均衡晶体管的第一电极彼此电连接，并且第二晶体管的第一电极和均衡晶体管的第二电极彼此电连接。

公开(公告)号：US07898886B2

公开(公告)日：2011-03-01

申请号：US12068983

申请日：2008-02-14

Applicant: Whee-jin Kwon ,  Jung-hwa Lee

Inventor： Whee-jin Kwon ,  Jung-hwa Lee

IPC: G11C7/02

CPC classification number: G11C7/065 ,  G11C7/12 ,  H01L27/0207 ,  H01L27/11803 ,  H01L29/66621

Abstract: A sense amplifier includes a first transistor having a gate electrode electrically connected to a bit line and a first electrode electrically connected to a complementary bit line. A second transistor has a gate electrode electrically connected to the complementary bit line and a first electrode electrically connected to the bit line. An equalizing transistor is disposed between the gate electrode of the first transistor and the gate electrode of the second transistor. The first electrode of the first transistor and a first electrode of the equalizing transistor are electrically connected to each other, and the first electrode of the second transistor and a second electrode of the equalizing transistor are electrically connected to each other.

Abstract translation: 读出放大器包括：第一晶体管，其具有电连接到位线的栅电极和与互补位线电连接的第一电极。 第二晶体管具有电连接到互补位线的栅电极和电连接到位线的第一电极。 在第一晶体管的栅电极和第二晶体管的栅电极之间设置均衡晶体管。 第一晶体管的第一电极和均衡晶体管的第一电极彼此电连接，并且第二晶体管的第一电极和均衡晶体管的第二电极彼此电连接。

公开(公告)号：US20090175105A1

公开(公告)日：2009-07-09

申请号：US12318685

申请日：2009-01-06

Applicant: Hyun-ki Kim ,  Whee-Jin Kwon

Inventor： Hyun-ki Kim ,  Whee-Jin Kwon

IPC: G11C29/00 ,  G11C8/00

CPC classification number: G11C29/28 ,  G11C2029/1202 ,  G11C2029/1802

Abstract: Example embodiments relate to a semiconductor memory device that includes an address coding method for a multi-word line test, for example, an address coding method to test a semiconductor memory device having a cell block row selection circuit. The semiconductor memory device may include a plurality of memory cell blocks, where each memory cell block may include memory cells coupled to a bit line. The method may include coding row addresses of the memory cell block by dividing one or more row addresses corresponding to cell blocks of the memory cell block to create sub-cell blocks and adding the sub-cell blocs into the main cell blocks to create a logical memory block, which enables word lines of the main cell blocks and sub-cell blocks at the same time.

Abstract translation: 示例性实施例涉及一种半导体存储器件，其包括用于多字线测试的地址编码方法，例如，用于测试具有单元块行选择电路的半导体存储器件的地址编码方法。 半导体存储器件可以包括多个存储器单元块，其中每个存储器单元块可以包括耦合到位线的存储器单元。 该方法可以包括通过划分与存储器单元块的单元块相对应的一个或多个行地址来编码存储器单元块的行地址以创建子单元块并将子单元块添加到主单元块中以创建逻辑 存储块，其同时启用主单元块和子单元块的字线。

公开(公告)号：US07990799B2

公开(公告)日：2011-08-02

申请号：US12318685

申请日：2009-01-06

Applicant: Hyun-Ki Kim ,  Whee-Jin Kwon

Inventor： Hyun-Ki Kim ,  Whee-Jin Kwon

IPC: G11C8/00

CPC classification number: G11C29/28 ,  G11C2029/1202 ,  G11C2029/1802

Abstract: Example embodiments relate to a semiconductor memory device that includes an address coding method for a multi-word line test, for example, an address coding method to test a semiconductor memory device having a cell block row selection circuit. The semiconductor memory device may include a plurality of memory cell blocks, where each memory cell block may include memory cells coupled to a bit line. The method may include coding row addresses of the memory cell block by dividing one or more row addresses corresponding to cell blocks of the memory cell block to create sub-cell blocks and adding the sub-cell blocs into the main cell blocks to create a logical memory block, which enables word lines of the main cell blocks and sub-cell blocks at the same time.

Abstract translation: 示例性实施例涉及一种半导体存储器件，其包括用于多字线测试的地址编码方法，例如，用于测试具有单元块行选择电路的半导体存储器件的地址编码方法。 半导体存储器件可以包括多个存储器单元块，其中每个存储器单元块可以包括耦合到位线的存储器单元。 该方法可以包括通过划分与存储器单元块的单元块相对应的一个或多个行地址来编码存储器单元块的行地址以创建子单元块并将子单元块添加到主单元块中以创建逻辑 存储块，其同时启用主单元块和子单元块的字线。