公开(公告)号：US20090147559A1

公开(公告)日：2009-06-11

申请号：US12326940

申请日：2008-12-03

申请人： Yun-Sang LEE ,  Woo-Jung SUN ,  Jung-Bae LEE

发明人： Yun-Sang LEE ,  Woo-Jung SUN ,  Jung-Bae LEE

IPC分类号： G11C11/4091 ,  G11C7/06

CPC分类号： G11C11/4091 ,  G11C7/065 ,  G11C7/12 ,  G11C11/4094

摘要： A memory cell array with open bit line structure includes a first sub memory cell array, a second sub memory cell array, a sense-amplifier/precharge circuit, first capacitors and second capacitors. The first sub memory cell array is activated in response to a first word line enable signal, and the second sub memory cell array is activated in response to a second word line enable signal. The sense-amplifier/precharge circuit is connected to the first sub memory cell array through first bit lines and to the second sub memory cell array through second bit lines, and the sense-amplifier/precharge circuit precharges the first bit lines and the second bit lines and amplifies data provided from the first sub memory cell array and the second sub memory cell array.

摘要翻译： 具有开放位线结构的存储单元阵列包括第一子存储单元阵列，第二子存储单元阵列，读出放大器/预充电电路，第一电容器和第二电容器。 第一子存储单元阵列响应于第一字线使能信号被激活，并且第二子存储单元阵列响应于第二字线使能信号被激活。 感测放大器/预充电电路通过第一位线连接到第一子存储单元阵列，并通过第二位线连接到第二子存储单元阵列，并且读出放大器/预充电电路对第一位线和第二位进行预充电 并且放大从第一子存储单元阵列和第二子存储单元阵列提供的数据。

公开(公告)号：US07894241B2

公开(公告)日：2011-02-22

申请号：US12326940

申请日：2008-12-03

申请人： Yun-Sang Lee ,  Woo-Jung Sun ,  Jung-Bae Lee

发明人： Yun-Sang Lee ,  Woo-Jung Sun ,  Jung-Bae Lee

IPC分类号： G11C7/00

CPC分类号： G11C11/4091 ,  G11C7/065 ,  G11C7/12 ,  G11C11/4094

摘要： A memory cell array with open bit line structure includes a first sub memory cell array, a second sub memory cell array, a sense-amplifier/precharge circuit, first capacitors and second capacitors. The first sub memory cell array is activated in response to a first word line enable signal, and the second sub memory cell array is activated in response to a second word line enable signal. The sense-amplifier/precharge circuit is connected to the first sub memory cell array through first bit lines and to the second sub memory cell array through second bit lines, and the sense-amplifier/precharge circuit precharges the first bit lines and the second bit lines and amplifies data provided from the first sub memory cell array and the second sub memory cell array.

摘要翻译： 具有开放位线结构的存储单元阵列包括第一子存储单元阵列，第二子存储单元阵列，读出放大器/预充电电路，第一电容器和第二电容器。 第一子存储单元阵列响应于第一字线使能信号被激活，并且第二子存储单元阵列响应于第二字线使能信号被激活。 感测放大器/预充电电路通过第一位线连接到第一子存储单元阵列，并通过第二位线连接到第二子存储单元阵列，并且读出放大器/预充电电路对第一位线和第二位进行预充电 并且放大从第一子存储单元阵列和第二子存储单元阵列提供的数据。