-
公开(公告)号：US07779381B2
公开(公告)日：2010-08-17
申请号：US11519381
申请日：2006-09-11
IPC分类号： G06F17/50
CPC分类号： G01R31/31721 , G01R31/31813 , G06F17/5045
摘要： In the field of integrated circuit design and testing, especially directed towards integrated circuits intended to operate at low power, a method and system are provided for circuit design and simulation and testing for mapping portions of a circuit, such as a power domain or portion of a power domain, to a test mode. Thereby only those portions of the circuit which need to be powered up in a particular test mode are powered up both in the design (simulation) phase and in the actual testing. This conserves power usage during actual testing as against powering up all portions of the circuit, which is not desirable during the testing of the circuit after manufacture. This ensures that the power conditions required to excite and observe any circuit faults during testing exist for the power conditions that are applied during, for instance, manufacturing testing. By automatically partitioning the faults to remove those that cannot be excited or observed during manufacturing and testing, the testability of the device in terms of its partitions or parts will accurately reflect the power state of the logic portions of the circuit.
摘要翻译： 在集成电路设计和测试领域，特别针对旨在以低功率运行的集成电路，提供了一种方法和系统，用于电路设计和仿真和测试，用于映射电路的部分，例如电源域或部分 电源域，进入测试模式。 因此，在设计（仿真）阶段和实际测试中只需要在特定测试模式下需要上电的电路的那些部分。 这节省了实际测试期间的功率使用，以防止电路的所有部分上电，这在制造后的电路测试期间是不期望的。 这确保了在测试过程中激发和观察任何电路故障所需的电源条件存在于例如制造测试期间应用的功率条件。 通过自动划分故障以去除在制造和测试期间不能激发或观察到的故障，器件在其分区或部件方面的可测试性将准确反映电路逻辑部分的功率状态。
-
公开(公告)号：US20080071513A1
公开(公告)日：2008-03-20
申请号：US11519381
申请日：2006-09-11
CPC分类号： G01R31/31721 , G01R31/31813 , G06F17/5045
摘要： In the field of integrated circuit design and testing, especially directed towards integrated circuits intended to operate at low power, a method and system are provided for circuit design and simulation and testing for mapping portions of a circuit, such as a power domain or portion of a power domain, to a test mode. Thereby only those portions of the circuit which need to be powered up in a particular test mode are powered up both in the design (simulation) phase and in the actual testing. This conserves power usage during actual testing as against powering up all portions of the circuit, which is not desirable during the testing of the circuit after manufacture. This ensures that the power conditions required to excite and observe any circuit faults during testing exist for the power conditions that are applied during, for instance, manufacturing testing. By automatically partitioning the faults to remove those that cannot be excited or observed during manufacturing and testing, the testability of the device in terms of its partitions or parts will accurately reflect the power state of the logic portions of the circuit.
摘要翻译： 在集成电路设计和测试领域，特别针对旨在以低功率运行的集成电路，提供了一种方法和系统，用于电路设计和仿真和测试，用于映射电路的部分，例如电源域或部分 电源域，进入测试模式。 因此，在设计（仿真）阶段和实际测试中只需要在特定测试模式下需要上电的电路的那些部分。 这节省了实际测试期间的功率使用，以防止电路的所有部分上电，这在制造后的电路测试期间是不期望的。 这确保了在测试过程中激发和观察任何电路故障所需的电源条件存在于例如制造测试期间应用的功率条件。 通过自动划分故障以去除在制造和测试期间不能激发或观察到的故障，器件在其分区或部件方面的可测试性将准确反映电路逻辑部分的功率状态。
-
搜索结果
2 条记录 (耗时 0.01 秒)
