公开(公告)号：US08555227B2

公开(公告)日：2013-10-08

申请号：US13197930

申请日：2011-08-04

Applicant: Yahia Mallem ,  Mickael Giroud ,  Lionel Jure

Inventor： Yahia Mallem ,  Mickael Giroud ,  Lionel Jure

IPC: G06F17/50

CPC classification number: G06F1/10

Abstract: The invention concerns a computer implemented method of circuit conception of a clock tree (200) comprising: a plurality of pulse generators (202) each being coupled to the input of one or more pulsed latches and being arranged to generate a pulsed signal (PS); and a tree of buffers (204) for supplying a clock signal (CLK) to the pulse generators, the method comprising: the conception of the clock tree without pulse generators based on a timing analysis by the computer of the propagation of clock edges in the clock tree; and replacing by the computer in the clock tree at least one buffer, coupled to the input of each pulsed latch, by a pulse generator.

Abstract translation: 本发明涉及一种计算机实现的时钟树（200）的电路概念的方法，包括：多个脉冲发生器（202），每个脉冲发生器（202）耦合到一个或多个脉冲锁存器的输入端，并被布置成产生脉冲信号（PS） ; 以及用于向脉冲发生器提供时钟信号（CLK）的缓冲器树（204），所述方法包括：基于由计算机对时钟沿的传播的脉冲发生器的时钟树的构思 时钟树 并且由时钟树中的计算机替换由脉冲发生器耦合到每个脉冲锁存器的输入的至少一个缓冲器。

公开(公告)号：US20120032721A1

公开(公告)日：2012-02-09

申请号：US13197930

申请日：2011-08-04

Applicant: Yahia MALLEM ,  Mickael GIROUD ,  Lionel JURE

Inventor： Yahia MALLEM ,  Mickael GIROUD ,  Lionel JURE

IPC: G06F1/04 ,  H05K13/00 ,  G06F17/50

CPC classification number: G06F1/10

Abstract: The invention concerns a computer implemented method of circuit conception of a clock tree (200) comprising: a plurality of pulse generators (202) each being coupled to the input of one or more pulsed latches and being arranged to generate a pulsed signal (PS); and a tree of buffers (204) for supplying a clock signal (CLK) to the pulse generators, the method comprising: the conception of the clock tree without pulse generators based on a timing analysis by the computer of the propagation of clock edges in the clock tree; and replacing by the computer in the clock tree at least one buffer, coupled to the input of each pulsed latch, by a pulse generator.

Abstract translation: 本发明涉及一种计算机实现的时钟树（200）的电路概念的方法，包括：多个脉冲发生器（202），每个脉冲发生器（202）耦合到一个或多个脉冲锁存器的输入端，并被布置成产生脉冲信号（PS） ; 以及用于向脉冲发生器提供时钟信号（CLK）的缓冲器树（204），所述方法包括：基于由计算机对时钟沿的传播的脉冲发生器的时钟树的构思 时钟树 并且由时钟树中的计算机替换由脉冲发生器耦合到每个脉冲锁存器的输入的至少一个缓冲器。