公开(公告)号：US07930673B2

公开(公告)日：2011-04-19

申请号：US12128554

申请日：2008-05-28

申请人： Yunjian (William) Jiang ,  Arvind Srinivasan ,  Joy Banerjee ,  Yinghua Li ,  Partha Das ,  Samit Chaudhuri

发明人： Yunjian (William) Jiang ,  Arvind Srinivasan ,  Joy Banerjee ,  Yinghua Li ,  Partha Das ,  Samit Chaudhuri

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F17/5031 ,  G06F2217/08

摘要： A power optimization method of deriving gated circuitry in a synthesized netlist of an integrated circuit (IC) design is provided. A block in the synthesized netlist is identified as an idle candidate block. Sub-blocks on the chip are clustered into a cluster. For the cluster, a clock gating structure optimized for power savings is determined, based on the idle candidate block. One or more inflexible clock gates are inserted in the netlist according to the clock gate structure.

摘要翻译： 提供了一种在集成电路（IC）设计的综合网表中导出门控电路的功率优化方法。 合成网表中的块被标识为空闲候选块。 芯片上的子块被聚集成一个集群。 对于集群，基于空闲候选块确定针对功率节省优化的时钟门控结构。 根据时钟门结构，在网表中插入一个或多个不灵活的时钟门。

公开(公告)号：US07882461B2

公开(公告)日：2011-02-01

申请号：US12128574

申请日：2008-05-28

申请人： Yunjian (William) Jiang ,  Arvind Srinivasan ,  Joy Banerjee ,  Yinghua Li ,  Partha Das ,  Samit Chaudhuri

发明人： Yunjian (William) Jiang ,  Arvind Srinivasan ,  Joy Banerjee ,  Yinghua Li ,  Partha Das ,  Samit Chaudhuri

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F17/5031 ,  G06F2217/08

摘要： A method of optimizing clock-gated circuitry in an integrated circuit (IC) design is provided. A plurality of signals which feed into enable inputs of a plurality of clock gates is determined, where the clock gates gate a plurality of sequential elements in the IC design. Combinational logic which is shared among the plurality of signals is identified. The clock-gated circuitry is transformed into multiple levels of clock-gating circuitry based on the shared combinational logic.

摘要翻译： 提供了一种在集成电路（IC）设计中优化时钟选通电路的方法。 确定馈送到多个时钟门的使能输入的多个信号，其中时钟门选通IC设计中的多个顺序元件。 识别在多个信号之间共享的组合逻辑。 时钟门控电路基于共享组合逻辑转换为多级时钟门控电路。

公开(公告)号：US20080301593A1

公开(公告)日：2008-12-04

申请号：US12128554

申请日：2008-05-28

申请人： Yunjian (William) Jiang ,  Arvind Srinivasan ,  Joy Banerjee ,  Yinghua Li ,  Partha Das ,  Samit Chaudhuri

发明人： Yunjian (William) Jiang ,  Arvind Srinivasan ,  Joy Banerjee ,  Yinghua Li ,  Partha Das ,  Samit Chaudhuri

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F17/5031 ,  G06F2217/08

摘要： A power optimization method of deriving gated circuitry in a synthesized netlist of an integrated circuit (IC) design is provided. A block in the synthesized netlist is identified as an idle candidate block. Sub-blocks on the chip are clustered into a cluster. For the cluster, a clock gating structure optimized for power savings is determined, based on the idle candidate block. One or more inflexible clock gates are inserted in the netlist according to the clock gate structure.

摘要翻译： 提供了一种在集成电路（IC）设计的综合网表中导出门控电路的功率优化方法。 合成网表中的块被标识为空闲候选块。 芯片上的子块被聚集成一个集群。 对于集群，基于空闲候选块确定针对功率节省优化的时钟门控结构。 根据时钟门结构，在网表中插入一个或多个不灵活的时钟门。

公开(公告)号：US07383522B2

公开(公告)日：2008-06-03

申请号：US11178111

申请日：2005-07-08

申请人： Rajeev Murgai ,  Yinghua Li ,  Takashi Miyoshi

发明人： Rajeev Murgai ,  Yinghua Li ,  Takashi Miyoshi

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： G06F17/5031

摘要： In one embodiment, a method for crosstalk-aware timing analysis includes accessing a design of a circuit and identifying critical paths in the design. Each critical path includes one or more victim interconnects and one or more cells. The method includes identifying potential aggressor interconnects associated with each victim interconnect and, for each victim interconnect, extracting parasitics of the victim interconnect and the potential aggressor interconnects associated with the victim interconnect. The method includes computing timing windows of the potential aggressor interconnects and computing a first timing of each cell and each victim interconnect on each critical path. The method also includes, for each critical path, generating timing waveforms of the potential aggressor interconnects, traversing the critical path from a start point on the critical path to an end point on the critical path, and, computing a second timing of each cell and each victim interconnect on the critical path according to a traversal of the critical path.

摘要翻译： 在一个实施例中，用于串扰感知定时分析的方法包括访问电路的设计并且识别设计中的关键路径。 每个关键路径包括一个或多个受害互连和一个或多个单元。 该方法包括识别与每个受害者互连相关联的潜在攻击者互连，并且针对每个受害者互连，提取受害者互连的寄生效应以及与受害者互连相关联的潜在攻击者互连。 该方法包括计算潜在的攻击者互连的定时窗口，并且计算每个小区的第一定时和每个关键路径上的每个受害者互连。 该方法还包括针对每个关键路径生成潜在攻击者互连的定时波形，遍历从关键路径上的起始点到关键路径上的终点的关键路径，以及计算每个小区的第二定时，以及 每个受害者根据关键路径的遍历在关键路径上进行互连。

公开(公告)号：US08434047B1

公开(公告)日：2013-04-30

申请号：US13013024

申请日：2011-01-25

申请人： Yunjian (William) Jiang ,  Arvind Srinivasan ,  Joy Banerjee ,  Yinghua Li ,  Partha Das ,  Samit Chaudhuri

发明人： Yunjian (William) Jiang ,  Arvind Srinivasan ,  Joy Banerjee ,  Yinghua Li ,  Partha Das ,  Samit Chaudhuri

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F17/5031 ,  G06F2217/08

摘要： A method of optimizing clock-gated circuitry in an integrated circuit (IC) design is provided. A plurality of signals which feed into enable inputs of a plurality of clock gates is determined, where the clock gates gate a plurality of sequential elements in the IC design. Combinational logic which is shared among the plurality of signals is identified. The clock-gated circuitry is transformed into multiple levels of clock-gating circuitry based on the shared combinational logic.

摘要翻译： 提供了一种在集成电路（IC）设计中优化时钟选通电路的方法。 确定馈送到多个时钟门的使能输入的多个信号，其中时钟门选通IC设计中的多个顺序元件。 识别在多个信号之间共享的组合逻辑。 时钟门控电路基于共享组合逻辑转换为多级时钟门控电路。

公开(公告)号：US20080301594A1

公开(公告)日：2008-12-04

申请号：US12128574

申请日：2008-05-28

申请人： Yunjian (William) Jiang ,  Arvind Srinivasan ,  Joy Banerjee ,  Yinghua Li ,  Partha Das ,  Samit Chaudhuri

发明人： Yunjian (William) Jiang ,  Arvind Srinivasan ,  Joy Banerjee ,  Yinghua Li ,  Partha Das ,  Samit Chaudhuri

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F17/5031 ,  G06F2217/08

摘要： A method of optimizing clock-gated circuitry in an integrated circuit (IC) design is provided. A plurality of signals which feed into enable inputs of a plurality of clock gates is determined, where the clock gates gate a plurality of sequential elements in the IC design. Combinational logic which is shared among the plurality of signals is identified. The clock-gated circuitry is transformed into multiple levels of clock-gating circuitry based on the shared combinational logic.

摘要翻译： 提供了一种在集成电路（IC）设计中优化时钟选通电路的方法。 确定馈送到多个时钟门的使能输入的多个信号，其中时钟门选通IC设计中的多个顺序元件。 识别在多个信号之间共享的组合逻辑。 时钟门控电路基于共享组合逻辑转换为多级时钟门控电路。

公开(公告)号：US20060080627A1

公开(公告)日：2006-04-13

申请号：US11178111

申请日：2005-07-08

申请人： Rajeev Murgai ,  Yinghua Li ,  Takashi Miyoshi

发明人： Rajeev Murgai ,  Yinghua Li ,  Takashi Miyoshi

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： G06F17/5031

摘要： In one embodiment, a method for crosstalk-aware timing analysis includes accessing a design of a circuit and identifying critical paths in the design. Each critical path includes one or more victim interconnects and one or more cells. The method includes identifying potential aggressor interconnects associated with each victim interconnect and, for each victim interconnect, extracting parasitics of the victim interconnect and the potential aggressor interconnects associated with the victim interconnect. The method includes computing timing windows of the potential aggressor interconnects and computing a first timing of each cell and each victim interconnect on each critical path. The method also includes, for each critical path, generating timing waveforms of the potential aggressor interconnects, traversing the critical path from a start point on the critical path to an end point on the critical path, and, computing a second timing of each cell and each victim interconnect on the critical path according to a traversal of the critical path.

摘要翻译： 在一个实施例中，用于串扰感知定时分析的方法包括访问电路的设计并且识别设计中的关键路径。 每个关键路径包括一个或多个受害互连和一个或多个单元。 该方法包括识别与每个受害者互连相关联的潜在攻击者互连，并且针对每个受害者互连，提取受害者互连的寄生效应以及与受害者互连相关联的潜在攻击者互连。 该方法包括计算潜在的攻击者互连的定时窗口，并且计算每个小区的第一定时和每个关键路径上的每个受害者互连。 该方法还包括针对每个关键路径生成潜在攻击者互连的定时波形，遍历从关键路径上的起始点到关键路径上的终点的关键路径，以及计算每个小区的第二定时，以及 每个受害者根据关键路径的遍历在关键路径上进行互连。