公开(公告)号：US08324705B2

公开(公告)日：2012-12-04

申请号：US12127629

申请日：2008-05-27

申请人： Chien-Shao Tang ,  Dah-Chuen Ho ,  Yu-Chang Jong ,  Zhe-Yi Wang ,  Yuh-Hwa Chang ,  Yogendra Yadav

发明人： Chien-Shao Tang ,  Dah-Chuen Ho ,  Yu-Chang Jong ,  Zhe-Yi Wang ,  Yuh-Hwa Chang ,  Yogendra Yadav

IPC分类号： H01L29/872

CPC分类号： H01L27/0629 ,  H01L29/0619 ,  H01L29/0649 ,  H01L29/872

摘要： An integrated circuit structure includes a semiconductor substrate; a first well region of a first conductivity type over the semiconductor substrate; a second well region of a second conductivity type opposite the first conductivity type encircling the first well region; and a metal-containing layer over and adjoining the first well region and extending over at least an inner portion of the second well region. The metal-containing layer and the first well region form a Schottky barrier. The integrated circuit structure further includes an isolation region encircling the metal-containing layer; and a third well region of the second conductivity type encircling at least a central portion of the first well region. The third well region has a higher impurity concentration than the second well region, and includes a top surface adjoining the metal-containing layer, and a bottom surface higher than bottom surfaces of the first and the second well regions.

摘要翻译： 集成电路结构包括半导体衬底; 半导体衬底上的第一导电类型的第一阱区; 与第一导电类型相反的第二导电类型的环绕第一阱区的第二阱区; 以及在所述第一阱区上并邻接所述第一阱区并且在所述第二阱区的至少内部部分上延伸的含金属层。 含金属层和第一阱区形成肖特基势垒。 所述集成电路结构还包括环绕所述含金属层的隔离区域; 以及第二导电类型的第三阱区域，其环绕至少第一阱区域的中心部分。 第三阱区域具有比第二阱区域更高的杂质浓度，并且包括邻近含金属层的顶表面和高于第一阱区域和第二阱区域的底表面的底表面。

公开(公告)号：US20090294865A1

公开(公告)日：2009-12-03

申请号：US12127629

申请日：2008-05-27

申请人： Chien-Shao Tang ,  Dah-Chuen Ho ,  Yu-Chang Jong ,  Zhe-Yi Wang ,  Yuh-Hwa Chang ,  Yogendra Yadav

发明人： Chien-Shao Tang ,  Dah-Chuen Ho ,  Yu-Chang Jong ,  Zhe-Yi Wang ,  Yuh-Hwa Chang ,  Yogendra Yadav

IPC分类号： H01L27/06

CPC分类号： H01L27/0629 ,  H01L29/0619 ,  H01L29/0649 ,  H01L29/872

摘要： An integrated circuit structure includes a semiconductor substrate; a first well region of a first conductivity type over the semiconductor substrate; a second well region of a second conductivity type opposite the first conductivity type encircling the first well region; and a metal-containing layer over and adjoining the first well region and extending over at least an inner portion of the second well region. The metal-containing layer and the first well region form a Schottky barrier. The integrated circuit structure further includes an isolation region encircling the metal-containing layer; and a third well region of the second conductivity type encircling at least a central portion of the first well region. The third well region has a higher impurity concentration than the second well region, and includes a top surface adjoining the metal-containing layer, and a bottom surface higher than bottom surfaces of the first and the second well regions.

摘要翻译： 集成电路结构包括半导体衬底; 半导体衬底上的第一导电类型的第一阱区; 与第一导电类型相反的第二导电类型的环绕第一阱区的第二阱区; 以及在所述第一阱区上并邻接所述第一阱区并且在所述第二阱区的至少内部部分上延伸的含金属层。 含金属层和第一阱区形成肖特基势垒。 所述集成电路结构还包括环绕所述含金属层的隔离区域; 以及第二导电类型的第三阱区域，其环绕至少第一阱区域的中心部分。 第三阱区域具有比第二阱区域更高的杂质浓度，并且包括邻近含金属层的顶表面和高于第一阱区域和第二阱区域的底表面的底表面。