公开(公告)号：US06835649B2

公开(公告)日：2004-12-28

申请号：US10161570

申请日：2002-06-03

Applicant: Wei-Cheng Lee ,  Wen-Chen Chien ,  Yu-Da Fan ,  Kuo-Yen Liu ,  Yu-Ching Chang

Inventor： Wei-Cheng Lee ,  Wen-Chen Chien ,  Yu-Da Fan ,  Kuo-Yen Liu ,  Yu-Ching Chang

IPC: H01L214763

CPC classification number: H01L21/76877

Abstract: Within a method for forming a microelectronic fabrication there is provided a substrate having formed thereover a patterned dielectric layer which defines a via. There is also formed within a lower portion of the via a tungsten stud layer having a recess thereabove within the via. There is also formed within the recess a patterned conductor capping layer formed of a conductor material other than tungsten. The patterned conductor capping layer may seal a void formed within the tungsten stud layer.

Abstract translation: 在用于形成微电子制造的方法中，提供了在其上形成限定通孔的图案化电介质层的衬底。 在通孔的下部还形成有在其内部具有通孔内的凹部的钨螺柱层。 在凹部内还形成有由钨以外的导体材料形成的图案化导体封盖层。 图案化的导体封盖层可以密封形成在钨钉层内的空隙。