公开(公告)号：US08180955B2

公开(公告)日：2012-05-15

申请号：US12705641

申请日：2010-02-15

申请人： Rong Li ,  Huaqiao Wang ,  Yuefeng Jin

发明人： Rong Li ,  Huaqiao Wang ,  Yuefeng Jin

IPC分类号： G06F12/00

CPC分类号： G06F12/0246 ,  G06F2212/7202 ,  G06F2212/7203

摘要： A computing system is provided. A flash memory device includes at least one mapping block, at least one modification block and at least one cache block. A processor is configured to perform: receiving a write command with a write logical address and predetermined data, loading content of a cache page from the cache block corresponding to the modification block according to the write logical address to a random access memory device in response to that a page of the mapping block corresponding to the write logical address has been used, the processor, reading orderly the content of the cache page stored in the random access memory device to obtain location information of an empty page of the modification block, and writing the predetermined data to the empty page according to the location information. Each cache page includes data fields to store location information corresponding to the data has been written in the pages of the modification block in order.

摘要翻译： 提供了一种计算系统。 闪存器件包括至少一个映射块，至少一个修改块和至少一个高速缓存块。 处理器被配置为执行：接收具有写入逻辑地址和预定数据的写入命令，根据所述写入逻辑地址从对应于所述修改块的高速缓存块将高速缓存页面的内容加载到随机存取存储器件中，以响应于 已经使用与写入逻辑地址对应的映射块的页面，处理器读取存储在随机存取存储器件中的高速缓存页的内容，以获得修改块的空页的位置信息，并写入 根据位置信息将预定数据提供给空页。 每个高速缓存页面包括用于存储与数据相对应的位置信息的数据字段已被按顺序写入修改块的页面。

公开(公告)号：US20100287327A1

公开(公告)日：2010-11-11

申请号：US12705641

申请日：2010-02-15

申请人： Rong Li ,  Huaqiao Wang ,  Yuefeng Jin

发明人： Rong Li ,  Huaqiao Wang ,  Yuefeng Jin

IPC分类号： G06F12/00 ,  G06F12/10 ,  G06F12/08

CPC分类号： G06F12/0246 ,  G06F2212/7202 ,  G06F2212/7203

摘要： A computing system is provided. A flash memory device includes at least one mapping block, at least one modification block and at least one cache block. A processor is configured to perform: receiving a write command with a write logical address and predetermined data, loading content of a cache page from the cache block corresponding to the modification block according to the write logical address to a random access memory device in response to that a page of the mapping block corresponding to the write logical address has been used, the processor, reading orderly the content of the cache page stored in the random access memory device to obtain location information of an empty page of the modification block, and writing the predetermined data to the empty page according to the location information. Each cache page includes data fields to store location information corresponding to the data has been written in the pages of the modification block in order.

摘要翻译： 提供了一种计算系统。 闪存器件包括至少一个映射块，至少一个修改块和至少一个高速缓存块。 处理器被配置为执行：接收具有写入逻辑地址和预定数据的写入命令，根据所述写入逻辑地址从对应于所述修改块的高速缓存块将高速缓存页面的内容加载到随机存取存储器件中，以响应于 已经使用与写入逻辑地址相对应的映射块的页面，处理器读取存储在随机存取存储器件中的高速缓存页的内容，以获得修改块的空页的位置信息，并写入 根据位置信息将预定数据提供给空页。 每个高速缓存页面包括用于存储与数据相对应的位置信息的数据字段已被按顺序写入修改块的页面。

公开(公告)号：US20100077135A1

公开(公告)日：2010-03-25

申请号：US12499859

申请日：2009-07-09

申请人： Rong Li ,  Yuefeng Jin ,  Li Wang

发明人： Rong Li ,  Yuefeng Jin ,  Li Wang

IPC分类号： G06F12/02 ,  G06F12/00

CPC分类号： G06F12/0246 ,  G06F2212/7211

摘要： A wear leveling method for a non-volatile memory is provided. The non-volatile memory includes a plurality of data blocks, each corresponding to a time value. The data blocks are arranged according to a sequence of the time values corresponding thereto. The arranged blocks form a key table. An erase operation is determined whether to be executed for the data blocks. When the erase operation is executed for the data blocks, the corresponding data block is erased according to a sequence of the time values of the data blocks in the key table.

摘要翻译： 提供了一种用于非易失性存储器的磨损均衡方法。 非易失性存储器包括多个数据块，每个数据块对应于时间值。 数据块根据与其对应的时间值的顺序排列。 排列的块形成关键表。 确定是否对数据块执行擦除操作。 当对数据块执行擦除操作时，根据密钥表中的数据块的时间值的顺序擦除对应的数据块。