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    Method for processing instant message in wireless terminal and wireless terminal implementing the same
    1.
    发明申请
    Method for processing instant message in wireless terminal and wireless terminal implementing the same 审中-公开
    在无线终端中处理即时消息的方法和实现相同的无线终端

    公开(公告)号：US20070055726A1

    公开(公告)日：2007-03-08

    申请号：US11376306

    申请日：2006-03-16

    申请人： Won-Sook Kwak ,  Yun-Jeong Choi

    发明人： Won-Sook Kwak ,  Yun-Jeong Choi

    IPC分类号： G06F15/16

    CPC分类号： H04M1/72547

    摘要： Method and wireless terminal which has a messenger service function, for executing the messenger service function when subscriber information for executing the messenger service function is input are provided. The instant message is generated according to execution of the messenger service function. The generated instant message is stored while applying identifier information corresponding to the subscriber information to the generated instant message, when an instant message storage key is operated.

    摘要翻译： 提供具有信使服务功能的方法和无线终端，用于在输入用于执行信使服务功能的用户信息时执行信使服务功能。 根据信使服务功能的执行生成即时消息。 当即时消息存储键被操作时，产生的即时消息被存储，同时将与用户信息相对应的标识符信息应用于生成的即时消息。

    Level shifter circuit of semiconductor memory device
    2.
    发明申请
    Level shifter circuit of semiconductor memory device 审中-公开
    半导体存储器件的电平移位电路

    公开(公告)号：US20070018710A1

    公开(公告)日：2007-01-25

    申请号：US11416437

    申请日：2006-05-02

    申请人： Yun-jeong Choi ,  Young-sun Min ,  Young-min Jang

    发明人： Yun-jeong Choi ,  Young-sun Min ,  Young-min Jang

    IPC分类号： H03L5/00

    CPC分类号： G11C5/14 ,  H03K3/012 ,  H03K3/356113

    摘要： A level shifter circuit of a semiconductor memory device prevents a leakage current from being generated in a deep power down mode. The level shifter circuit comprises: a first NMOS transistor connected between a first node and a ground voltage terminal, wherein an input signal, which has a voltage level that is one of the ground voltage and a first power supply voltage, is input to a gate of the first NMOS transistor; a second NMOS transistor connected between a second node and the ground voltage terminal, wherein an inverted signal of the input signal is input to a gate of the second NMOS transistor; a first PMOS transistor which is connected between the first node and a second power supply voltage terminal and has a gate connected to the second node; a second PMOS transistor which is connected between the second node and the second power supply voltage terminal and has a gate connected to the first node; and a third NMOS transistor which has a drain connected to one of the first node and the second node and a gate connected to the other one of the first node and the second node and which maintains the first node and the second node each at one of two high and low logic levels when operating in a reduced power mode.

    摘要翻译： 半导体存储器件的电平移动器电路防止在深度掉电模式中产生漏电流。 电平移位器电路包括：连接在第一节点和接地电压端子之间的第一NMOS晶体管，其中具有作为接地电压和第一电源电压之一的电压电平的输入信号被输入到门 的第一NMOS晶体管; 连接在第二节点和接地电压端子之间的第二NMOS晶体管，其中输入信号的反相信号被输入到第二NMOS晶体管的栅极; 第一PMOS晶体管，其连接在第一节点和第二电源电压端子之间，并具有连接到第二节点的栅极; 第二PMOS晶体管，其连接在第二节点和第二电源电压端子之间，并具有连接到第一节点的栅极; 以及第三NMOS晶体管，其具有连接到所述第一节点和所述第二节点中的一个的漏极，以及连接到所述第一节点和所述第二节点中的另一节点的栅极，并且将所述第一节点和所述第二节点分别维持在 在降低功耗模式下工作时的两个高低逻辑电平。