公开(公告)号：US06373910B1

公开(公告)日：2002-04-16

申请号：US09765158

申请日：2001-01-17

申请人： Samuel C Kingston ,  Steven T Barham ,  Alan E Lundquist ,  W. Paul Willes ,  Raied Naji Mazahreh ,  Ronald S Leahy ,  Zackary C Bagley

发明人： Samuel C Kingston ,  Steven T Barham ,  Alan E Lundquist ,  W. Paul Willes ,  Raied Naji Mazahreh ,  Ronald S Leahy ,  Zackary C Bagley

IPC分类号： H04B110

CPC分类号： H03H17/0294 ,  H04L25/03006

摘要： An integrated circuit includes a reconfigurable FIR filter has an input port for receiving digital input signals and an output coupled to a coherent signal processor and a coherent memory. The FIR filter programmably provides filtered signals to the coherent signal processor for storage in the coherent memory. The integrated circuit further includes a sequential weight processor having an input coupled to an output of the coherent memory. The sequential weight processor includes a weight memory and operates to output symbol soft decision data resulting from processing the digital input signals. The integrated circuit is programmable into one of a plurality of operating modes, including at least one of a received signal acquisition mode, a channel estimator mode, an adaptive equalizer mode, and a channel-wise differential mode.

摘要翻译： 集成电路包括可重构FIR滤波器，具有用于接收数字输入信号的输入端口和耦合到相干信号处理器和相干存储器的输出。 FIR滤波器可编程地将经滤波的信号提供给相干信号处理器以存储在相干存储器中。 集成电路还包括具有耦合到相干存储器的输出的输入的顺序权重处理器。 顺序加权处理器包括权重存储器，并且操作以输出由处理数字输入信号得到的符号软判决数据。 集成电路可编程为多种操作模式之一，包括接收信号采集模式，信道估计模式，自适应均衡器模式和频道方式差分模式中的至少一种。

公开(公告)号：US06201843B1

公开(公告)日：2001-03-13

申请号：US09257436

申请日：1999-02-25

申请人： Samuel C Kingston ,  Steven T Barham ,  Alan E Lundquist ,  W. Paul Willes ,  Raied Naji Mazahreh ,  Ronald S Leahy ,  Zackary C Bagley

发明人： Samuel C Kingston ,  Steven T Barham ,  Alan E Lundquist ,  W. Paul Willes ,  Raied Naji Mazahreh ,  Ronald S Leahy ,  Zackary C Bagley

IPC分类号： H04B110

CPC分类号： H03H17/0294 ,  H04L25/03006

摘要： An integrated circuit includes a reconfigurable FIR filter has an input port for receiving digital input signals and an output coupled to a coherent signal processor and a coherent memory. The FIR filter programmably provides filtered signals to the coherent signal processor for storage in the coherent memory. The integrated circuit further includes a sequential weight processor having an input coupled to an output of the coherent memory. The sequential weight processor includes a weight memory and operates to output symbol soft decision data resulting from processing the digital input signals. The integrated circuit is programmable into one of a plurality of operating modes, including at least one of a received signal acquisition mode, a channel estimator mode, an adaptive equalizer mode, and a channel-wise differential mode.

摘要翻译： 集成电路包括可重构FIR滤波器，具有用于接收数字输入信号的输入端口和耦合到相干信号处理器和相干存储器的输出。 FIR滤波器可编程地将经滤波的信号提供给相干信号处理器以存储在相干存储器中。 集成电路还包括具有耦合到相干存储器的输出的输入的顺序权重处理器。 顺序加权处理器包括权重存储器，并且操作以输出由处理数字输入信号得到的符号软判决数据。 集成电路可编程为多种操作模式之一，包括接收信号采集模式，信道估计模式，自适应均衡器模式和频道方式差分模式中的至少一种。