公开(公告)号：US4817028A

公开(公告)日：1989-03-28

申请号：US935996

申请日：1986-11-26

申请人： Jacques L. R. Masson ,  Zdenek Picel

发明人： Jacques L. R. Masson ,  Zdenek Picel

IPC分类号： G06F7/506 ,  G06F7/53 ,  G06F7/533 ,  G06F7/552 ,  G06F7/38

CPC分类号： G06F7/552 ,  G06F2207/5523

摘要： This device for summing squares is designed to calculate the sum of the squares of "n" numbers with "m" binary elements, where n and m are whole numbers equal to or greater than "2"; it is made up from a systolic network 14 formed of identical cells arranged in lines and columns and around which is arranged a first peripheral circuit 16 to supply signals to the upper line, a second peripheral circuit 18 to supply signals to the input column also receiving signals from a presentation circuit 20 acting as an interface between the "n" numbers and the systolic network and finally an output circuit 22 connected to the lower line. Each line of the network is allocated to the calculation of the square of each of the numbers. Calculations are carried forward from the upper to the lower line via links between the lines. The output circuit consists of an adder component supplying the result from the calculations brought forward from the last line.

摘要翻译： 用于求和平方的装置被设计为计算“n”个数与“m”个二进制元素的平方和，其中n和m是等于或大于“2”的整数; 它由从线和列布置的相同单元形成的收缩网络14构成，并且围绕它布置有第一外围电路16以向上行提供信号;第二外围电路18，用于向输入列提供信号，还接收 来自演示电路20的信号用作“n”号和收缩网络之间的接口，最后是连接到下线的输出电路22。 网络的每一行分配给每个数字的平方的计算。 通过线路之间的连接，从上到下连续进行计算。 输出电路由一个加法器部件组成，提供从最后一行提取的计算结果。

公开(公告)号：US4799179A

公开(公告)日：1989-01-17

申请号：US822503

申请日：1986-01-27

申请人： Jacques L. R. Masson ,  Zdenek Picel

发明人： Jacques L. R. Masson ,  Zdenek Picel

IPC分类号： H03H17/02 ,  H03H17/06 ,  G06F7/38

CPC分类号： H03H17/0266

摘要： In a signal analysing and synthesizing filter bank system, the analysing bank receives a signal sampled at the rate f.sub.e and produces N contiguous subbank signals sampled at the rate f.sub.e /N. From the subband signals the synthesizing bank must recover the incoming signal. These filter banks are formed by modulation of a prototype filter by sinusoidal signals which, for subband k (O.ltoreq.k.ltoreq.N=1), have a frequency (2k30 1)f.sub.e /(4N) and respective phases +(2k+1).pi./4 and -(2k+1).pi./4 for the analysing and synthesizing banks. These signals are furthermore delayed by a time delay (N.sub.c -1)/2f.sub.e), where N.sub.c is the number of coefficients of the prototype filter. Preferably, the analysing bank is realized by the cascade arrangement of an N-branch polyphase network (12) and a double-odd discrete cosine transform calculating arrangement (14) and the synthesizing bank is realized by the cascade arrangement of a double-odd discrete cosine transform calculating arrangement (15) and an N-branch polyphase network (17).

摘要翻译： 在信号分析和合成滤波器组系统中，分析组接收以速率fe采样的信号，并产生以速率fe / N采样的N个连续的子行信号。 从子带信号中，合成器必须恢复输入信号。 这些滤波器组通过正弦信号调制原型滤波器形成，对于子带k（0≤k≤N= 1），具有频率（2k30 1）fe /（4N）和相位相位 2k + 1）pi / 4和 - （2k + 1）pi / 4用于分析和合成银行。 这些信号进一步延迟了时间延迟（Nc-1）/ 2fe），其中Nc是原型滤波器的系数数。 优选地，通过N分支多相网络（12）和双奇数离散余弦变换计算装置（14）的级联布置实现分析库，并且通过双奇数离散化的级联布置来实现合成库 余弦变换计算装置（15）和N分支多相网络（17）。