公开(公告)号：US20040001489A1

公开(公告)日：2004-01-01

申请号：US10180874

申请日：2002-06-26

申请人： ADTRAN, INC

发明人： Clarke Edgar Moore ,  Marty Lee Pannell ,  W. Stuart Venters ,  Zachrey Lee Whaley II

IPC分类号： H04L012/28

CPC分类号： H04L12/5601 ,  H04L2012/5675

摘要： A bidirectional serial TDM backplanenullUTOPIA interface contains an ATM cell boundary location and transmit flow control mechanism, to provide for the efficient capture and storage of ATM cells from a serial TDM channel. Once stored in a transmit buffer, individual ATM cells are controllably read out for application to a downstream UTOPIA interface. In the upstream direction from the UTOPIA bus toward the serial TDM backplane, ATM cells are stored in a multi-cell receive buffer, so that they may be serialized for application to the TDM backplane. In the absence of ATM data cells to transfer, unfilled timeslots are filled with idle cells to maintain the ATM bus active.

摘要翻译： 双向串行TDM背板 - UTOPIA接口包含ATM信元边界位置和发送流控制机制，以提供从串行TDM信道有效捕获和存储ATM信元。 一旦存储在发送缓冲器中，可控制地读出单个ATM信元以供应用于下游UTOPIA接口。 在从UTOPIA总线朝向串行TDM背板的上行方向上，ATM信元被存储在多小区接收缓冲器中，使得它们可以被串行化以应用于TDM背板。 在没有ATM数据信元传输的情况下，未填充的时隙充满空闲信元，以维持ATM总线的有效。

公开(公告)号：US20040131088A1

公开(公告)日：2004-07-08

申请号：US10338461

申请日：2003-01-08

申请人： ADTRAN, INC.

发明人： Clarke Edgar Moore ,  Dwight Edwin Wright

IPC分类号： H04J003/12

CPC分类号： H04J3/1623 ,  H04J3/12 ,  H04J3/1635

摘要： A shared T1/E1 signaling bit processor interfaces with either T1 or E1 traffic, and controllably performs robbed bit signal extraction and insertion for T1/E1 signaling protocol using a common set of input/output circuitry and associated decode/control logic therefor. A receiver subsystem controllably samples and extracts signaling bits from selected time slots within serial frames of data incoming from the network to the DTE for delivery to the control processor; a transmitter subsystem controllably inserts signaling bits into selected signaling channels of serial frames of data outgoing from the DTE to the network.

摘要翻译： 共享的T1 / E1信令位处理器与T1或E1流量相连接，并且可以使用一组通用的输入/输出电路和相关的解码/控制逻辑控制执行T1 / E1信号协议的抢占位信号提取和插入。 接收机子系统可控地从从网络到DTE的数据的串行帧内的选定时隙中采样和提取信令比特，用于传送到控制处理器; 发射机子系统可控制地将信令比特插入到从DTE传出到网络的串行数据帧的选择的信令信道中。

公开(公告)号：US20040131049A1

公开(公告)日：2004-07-08

申请号：US10338445

申请日：2003-01-08

申请人： ADTRAN, INC.

发明人： Charles David Capps ,  Clarke Edgar Moore ,  Dwight Edwin Wright

IPC分类号： H04L012/66

CPC分类号： H04L12/66

摘要： A programmable network-DTE interface integrates T1/E1 framer, data pump and microprocessor components into a common subsystem chip architecture, and interfaces each of these components by means of a user programmable multiplexing subsystem, so as to allow any of the functional blocks of the architecture to be selectively enabled or disabled/by-passed by the user.

摘要翻译： 可编程网络DTE接口将T1 / E1成帧器，数据泵和微处理器部件集成到公共子系统芯片架构中，并通过用户可编程多路复用子系统对这些组件中的每一个进行接口，以便允许任何功能块 架构被用户有选择地启用或禁用/旁路。