公开(公告)号：US10720339B2

公开(公告)日：2020-07-21

申请号：US16300538

申请日：2017-04-27

Applicant: AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCH

Inventor： Masaya Kawano ,  Ka Fai Chang

IPC: H01L21/56 ,  H01L23/31 ,  H01L23/00 ,  H01L23/60

Abstract: A fan-out wafer-level packaging method and the package produced thereof are provided in the present application. The method comprises steps including: providing a silicon substrate layer having a first thickness; forming one or more active/passive devices comprising at least sources and drains and one or more diffusion layers adjoining the sources and drains, wherein forming the one or more active/passive devices comprises forming the sources and the drains in a front-end-of-line (FEOL) layer on a first side of the silicon substrate layer while forming the one or more diffusion layers at locations in the silicon substrate layer adjoining the sources and the drains; forming a redistribution layer (RDL) over the FEOL layer by copper damascene formation of multiple metallization layers for connecting the one or more active/passive devices to the one or more IC dies when the one or more IC dies are mounted on a side of the RDL opposite the FEOL layer; thinning the silicon substrate layer to a second thickness to form a thinned silicon substrate, the thinned silicon substrate comprising at least the one or more diffusion layers; and patterning the thinned silicon substrate to form one or more silicon regions, each of the one or more silicon regions comprising the one or more diffusion layers.