公开(公告)号：US20240063795A1

公开(公告)日：2024-02-22

申请号：US18108624

申请日：2023-02-12

Applicant: APPLE INC.

Inventor： Andrew Russell ,  Michael A. Dreesen ,  Adam Johnson ,  Jacek R. Wiatrowski

IPC: H03K19/003 ,  G01R31/3177

CPC classification number: H03K19/00315 ,  G01R31/3177

Abstract: An electronic circuit for dynamic evaluation of logic functions includes a discharging circuit, a first keeper circuit, a delay circuit and a second keeper circuit. The discharging circuit is configured to discharge an evaluation node. The first keeper circuit is configured to charge the evaluation node and configured to be disabled responsively to a first keeper control indication. The delay circuit is configured to generate a second keeper control indication that is delayed relative to the first keeper control indication. The second keeper circuit is configured to retain a charge on the evaluation node responsively to the second keeper control indication.