Testing a Hardware Emulation Model of a Circuit with Software Checker Routines Designed for an RTL Model of the Circuit
    1.
    发明申请
    Testing a Hardware Emulation Model of a Circuit with Software Checker Routines Designed for an RTL Model of the Circuit 审中-公开
    使用针对电路RTL模型设计的软件检查程序来测试电路的硬件仿真模型

    公开(公告)号:US20140100841A1

    公开(公告)日:2014-04-10

    申请号:US13647742

    申请日:2012-10-09

    Applicant: APPLE INC.

    CPC classification number: G06F17/5027

    Abstract: A hardware emulation system may emulate a plurality of cycles of a circuit, and may store state information at each cycle which specifies signal values for one or more signals of the circuit. After the hardware emulation has finished, the state information may be streamed from the memory of the hardware emulation system to a different storage device that is accessible by a computer system that executes one or more software checker routines. The computer system may execute the software checker routines, which may include passing the signal values specified in the state information to the software checker routines on a cycle-by-cycle basis similarly as if the software checker routines were receiving them in real time directly from the hardware emulation system.

    Abstract translation: 硬件仿真系统可以模拟电路的多个周期,并且可以在每个周期存储指定电路的一个或多个信号的信号值的状态信息。 在硬件仿真完成之后,状态信息可以从硬件仿真系统的存储器流传输到由执行一个或多个软件检查程序的计算机系统可访问的不同的存储设备。 计算机系统可以执行软件检查程序,其可以包括将状态信息中指定的信号值逐个循环地传递给软件检查程序,类似于软件检查程序直接从 硬件仿真系统。

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