PACKAGE PROGRAMMABLE DECOUPLING CAPACITOR ARRAY
    1.
    发明申请
    PACKAGE PROGRAMMABLE DECOUPLING CAPACITOR ARRAY 有权
    包装可编程电容器阵列

    公开(公告)号:US20170063355A1

    公开(公告)日:2017-03-02

    申请号:US14838778

    申请日:2015-08-28

    CPC classification number: H03K5/1252 H01L23/50 H01L23/5223 H01L23/525

    Abstract: A semiconductor chip allows for a selected amount of on-die decoupling capacitance to be connected to a very-large-scale integrated circuit (VLSI) system after the circuit design is complete. The semiconductor chip comprises an integrated circuit disposed on a packaging substrate, and a power distribution network that is electrically connectable to the integrated circuit via a programmable connectivity array via the packaging substrate.

    Abstract translation: 在电路设计完成之后,半导体芯片允许选定数量的管芯上的去耦电容连接到大规模集成电路(VLSI)系统。 半导体芯片包括设置在封装基板上的集成电路,以及经由可编程连接阵列经由封装基板与集成电路电连接的配电网。

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