公开(公告)号：US10095518B2

公开(公告)日：2018-10-09

申请号：US14941840

申请日：2015-11-16

Applicant: ARM LIMITED

Inventor： Andrew James Antony Lees ,  Ian Michael Caulfield ,  Peter Richard Greenhalgh

IPC: G06F9/30

Abstract: Instruction queue circuitry maintains an instruction queue to store fetched instructions. Instruction decode circuitry decodes instructions dispatched from the queue. The instruction decode circuitry allocates processor resource(s) for use in execution of the decoded instruction. Detection circuitry detect, for an instruction to be dispatched from a given instruction queue, a prediction indicating whether sufficient processor resources are predicted to be available for allocation to that instruction by the instruction decode circuitry. Dispatch circuitry dispatches an instruction from the queue to the instruction decode circuitry and allows deletion of the dispatched instruction from that instruction queue when the prediction indicates that sufficient processor resources are predicted to be available for allocation to that instruction by the instruction decode circuitry.

公开(公告)号：US10296349B2

公开(公告)日：2019-05-21

申请号：US14989841

申请日：2016-01-07

Applicant: ARM LIMITED

Inventor： Vladimir Vasekin ,  Antony John Penton ,  Chiloda Ashan Senarath Pathirane ,  Andrew James Antony Lees

IPC: G06F9/38

Abstract: Data processing circuitry comprises allocation circuitry to allocate one or more source and destination processor registers, of a set of processor registers each defined by a respective register index, to a processor instruction for use in execution of that processor instruction and to associate, with the processor instruction, information to indicate the register index of the allocated source and destination processor registers; the avocation circuitry being selectively operable to allocate, to a processor instruction, a group of destination processor registers having a subset of their register indices in common and to associate, with the processor instruction, information to indicate the register index of one processor register of the group and identifying information to identify one or more bits of the register index which differ between the processor registers in the allocated group of processor registers.