公开(公告)号：US20190213141A1

公开(公告)日：2019-07-11

申请号：US16242912

申请日：2019-01-08

Applicant: Apical Ltd ,  Arm Limited

Inventor： Metin Gokhan ÜNAL ,  Kushan Vijaykumar VYAS ,  Robert SHORTER ,  Mario Jose DAVID MANZANO

IPC: G06F12/121 ,  G06T1/60

CPC classification number: G06F12/121 ,  G06F2212/1021 ,  G06F2212/1044 ,  G06T1/60

Abstract: A method comprising, in an image processing operation, identifying location data indicative of a read path for the image processing operation, the read path at least partly traversing a block of pixels of an image. Parameter data relating to a characteristic of the read path in the context of the block is generated from the location. Storage prioritization data is associated with the block at least partly on the basis of the parameter data. The storage prioritization data is for determining whether block data representative of the block is to be evicted from storage.

公开(公告)号：US20160217592A1

公开(公告)日：2016-07-28

申请号：US15067683

申请日：2016-03-11

Applicant: ARM LIMITED

Inventor： Daren CROXFORD ,  Sharjeel SAEED ,  Kushan Vijaykumar VYAS

IPC: G06T11/00 ,  G06T1/60 ,  G06T1/20

CPC classification number: G06T11/00 ,  G06T1/20 ,  G06T1/60 ,  G06T11/40 ,  G06T11/60 ,  G06T15/005 ,  G06T2210/32 ,  G06T2210/62

Abstract: Apparatus and a corresponding method for processing image data are provided. The apparatus has compositing circuitry to generate a composite layer for a frame for display from image data representing plural layers of content within the frame. Plural latency buffers are provided to store at least a portion of the image data representing the plural layers. At least one of the plural latency buffers is larger than at least one other of the plural latency buffers. The compositing circuitry is responsive to at least one characteristic of the plural layers of content to allocate the plural layers to respective latency buffers of the plural latency buffers. Image data information for a layer allocated to the larger latency buffer is available for analysis earlier than that of the layers allocated to the smaller latency buffers and processing efficiencies can then result.

Abstract translation: 提供了用于处理图像数据的装置和相应的方法。 该装置具有合成电路，以从表示帧内的多层内容的图像数据生成用于显示帧的复合层。 提供多个延迟缓冲器以存储表示多个层的图像数据的至少一部分。 多个延迟缓冲器中的至少一个大于多个等待时间缓冲器中的至少一个。 合成电路响应于多层内容的至少一个特征，以将多个层分配给多个等待时间缓冲器的各个延迟缓冲器。 分配给较大等待时间缓冲器的图像的图像数据信息可以比分配给较小等待时间缓冲器的层的图像数据信息更早地进行分析，然后可以产生处理效率。