公开(公告)号：US10120808B2

公开(公告)日：2018-11-06

申请号：US15135916

申请日：2016-04-22

Applicant: ARM LIMITED

Inventor： Gergely Kiss ,  Gábor Móricz ,  Man Cheung Joseph Yiu

IPC: G06F13/36 ,  G06F12/0879 ,  G06F13/28 ,  G06F12/0893

Abstract: A data processing system includes interconnect circuitry providing a plurality of memory transaction paths between one or more transaction masters, including a processor, debugging circuitry and a DMA unit, and one or more transaction slaves including a non-volatile memory, a DRAM memory and an I/O interface. A cache memory is provided between the interconnect circuitry and the non-volatile memory. This cache memory may be a two way set associative cache memory. The cache memory may serve as a read-only cache memory. A cache miss will result in a line fill of a cache line including the target data which was missed. If prefetching is enabled for the cache memory and the transaction was attempting to read a program instruction, then a prefetch operation may be performed in which a further contiguous cache line of data is also fetched into the cache memory upon the cache miss.