公开(公告)号：US10162762B2

公开(公告)日：2018-12-25

申请号：US14692959

申请日：2015-04-22

Applicant: ARM LIMITED

Inventor： Geoffrey Blake ,  Ali Ghassan Saidi ,  Mitchell Hayenga

IPC: G06F12/1027

Abstract: A data processing system 4 includes a translation lookaside buffer 6 storing mapping data entries 10 indicative of virtual-to-physical address mappings for different regions of physical addresses. A hint generator 20 coupled to the translation lookaside buffer 6 generates hint data in dependence upon the storage of mapping data entries within the translation lookaside buffer 6. The hint generator 20 tracks the loading of mapping data entries and the eviction of mapping data entries from the translation lookaside buffer 6. The hint data is supplied to a memory controller 8 which controls how data corresponding to respective different regions of physical addresses is stored within a heterogeneous memory system, e.g. the power state of different portions of the memories storing different regions, which type of memory is used to store different regions.